ICCAD-2005 International Conference on Computer Aided Design
Nov. 6 2005 to Nov. 10 2005
San Jose, CA, USA
Table of Contents
Session 1A - Memory and arithmetic optimizations
Session 1A - Memory and arithmetic optimizations
Session 1A - Memory and arithmetic optimizations
Session 1B - Design manufacturing interaction
Session 1B - Design manufacturing interaction
Session 1B - Design manufacturing interaction
Session 1C - Detailed placement
Session 1D - Digital, analog and RF test
Session 1D - Digital, analog and RF test
Session 1D - Digital, analog and RF test
Session 1D - Digital, analog and RF test
Session 1D - Digital, analog and RF test
Session 2A - Embedded turorial: design trends
Session 2A - Embedded turorial: design trends
Session 2A - Embedded turorial: design trends
Session 2B - Physical design for manufacturing
Session 2B - Physical design for manufacturing
Session 2B - Physical design for manufacturing
Session 2C - Large-scale layout techniques
Session 2C - Large-scale layout techniques
Session 2C - Large-scale layout techniques
Session 2D - Novel ideas and logic synthesis
Session 2D - Novel ideas and logic synthesis
Session 3A - Embedded tutorial: opportunities and challenges with double-gated devices
Session 3A - Embedded tutorial: opportunities and challenges with double-gated devices
Session 3A - Embedded tutorial: opportunities and challenges with double-gated devices
Session 3A - Embedded tutorial: opportunities and challenges with double-gated devices
Session 3B - Routing and application specific NoC architectures
Session 3B - Routing and application specific NoC architectures
Session 3B - Routing and application specific NoC architectures
Session 3B - Routing and application specific NoC architectures
Session 3C - Memory driven code and architecture optimizations
Session 3C - Memory driven code and architecture optimizations
Session 3C - Memory driven code and architecture optimizations
Session 3C - Memory driven code and architecture optimizations
Session 3D - Exploiting arithmetic constructs in verification
Session 3D - Exploiting arithmetic constructs in verification
Session 3D - Exploiting arithmetic constructs in verification
Session 3D - Exploiting arithmetic constructs in verification
Session 4A - Buffers and voltage islands
Session 4A - Buffers and voltage islands
Session 4A - Buffers and voltage islands
Session 4B - Sequential circuit optimization
Session 4B - Sequential circuit optimization
Session 4C - Power grid verification
Session 4C - Power grid verification
Session 4C - Power grid verification
Session 4D - Nanoelectronics
Session 4D - Nanoelectronics
Session 5A - Variability in design
Session 5A - Variability in design
Session 5B - Efficient analog design space exploration techniques
Session 5B - Efficient analog design space exploration techniques
Session 5B - Efficient analog design space exploration techniques
Session 5C - Dynamic voltage scaling
Session 5C - Dynamic voltage scaling
Session 5C - Dynamic voltage scaling
Session 5C - Dynamic voltage scaling
Session 5D - Biochips and DNA-Based nanofabrication
Session 5D - Biochips and DNA-Based nanofabrication
Session 6A - Efficient simulation and synthesis methodologies for analog circuits
Session 6A - Efficient simulation and synthesis methodologies for analog circuits
Session 6B - Technology mapping and timing analysis
Session 6B - Technology mapping and timing analysis
Session 6B - Technology mapping and timing analysis
Session 6C - Power aware system architecture and software optimizations
Session 6C - Power aware system architecture and software optimizations
Session 6C - Power aware system architecture and software optimizations