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2010 IEEE/ACM International Conference on Computer-Aided Design (ICCAD 2010)

Nov. 7 2010 to Nov. 11 2010

San Jose, CA

Table of Contents

[Front matter]Freely available from IEEE.pp. 1-2
Executive CommitteeFreely available from IEEE.pp. 1-5
ForewordFreely available from IEEE.pp. 1-1
AwardsFreely available from IEEE.pp. 1-1
Keynote addressFull-text access may be available. Sign in or learn about subscription options.pp. 1-2
Table of contentsFreely available from IEEE.pp. 1-12
Author indexFreely available from IEEE.pp. 1-10
Fidelity metrics for estimation modelsFull-text access may be available. Sign in or learn about subscription options.pp. 1-8
by Haris Javaid, Aleksander Ignjatovic, Sri Parameswaran
Fast performance evaluation of fixed-point systems with un-smooth operatorsFull-text access may be available. Sign in or learn about subscription options.pp. 9-16
by K. Parashar, D. Menard, R. Rocher, O. Sentieys, D. Novo, F. Catthoor
Variation-aware layout-driven scheduling for performance yield optimizationFull-text access may be available. Sign in or learn about subscription options.pp. 17-24
by Gregory Lucas, Deming Chen
Analysis and optimization of SRAM robustness for double patterning lithographyFull-text access may be available. Sign in or learn about subscription options.pp. 25-31
by Vivek Joshi, Kanak Agarwal, David Blaauw, Dennis Sylvester
WISDOM: Wire spreading enhanced decomposition of masks in Double Patterning LithographyFull-text access may be available. Sign in or learn about subscription options.pp. 32-38
by Kun Yuan, David Z. Pan
Maximum-information storage system: Concept, implementation and applicationFull-text access may be available. Sign in or learn about subscription options.pp. 39-46
by Xin Li
Multi-Wafer Virtual Probe: Minimum-cost variation characterization by exploring wafer-to-wafer correlationFull-text access may be available. Sign in or learn about subscription options.pp. 47-54
by Wangyang Zhang, Xin Li, Emrah Acar, Frank Liu, Rob Rutenbar
On behavioral model equivalence checking for large analog/mixed signal systemsFull-text access may be available. Sign in or learn about subscription options.pp. 55-61
by Amandeep Singh, Peng Li
An algorithm for exploiting modeling error statistics to enable robust analog optimizationFull-text access may be available. Sign in or learn about subscription options.pp. 62-69
by Ashish Kumar Singh, Mario Lok, Kareem Ragab, Constantine Caramanis, Michael Orshansky
A simple implementation of determinant decision diagramFull-text access may be available. Sign in or learn about subscription options.pp. 70-76
by Guoyong Shi
Aging analysis at gate and macro cell levelFull-text access may be available. Sign in or learn about subscription options.pp. 77-84
by Dominik Lorenz, Martin Barke, Ulf Schlichtmann
Resilient microprocessor design for improving performance and energy efficiencyFull-text access may be available. Sign in or learn about subscription options.pp. 85-88
by Keith A. Bowman, James W. Tschanz
Process variation aware performance modeling and dynamic power management for multi-core systemsFull-text access may be available. Sign in or learn about subscription options.pp. 89-92
by Siddharth Garg, Diana Marculescu, Sebastian X. Herbert
Design-aware mask inspectionFull-text access may be available. Sign in or learn about subscription options.pp. 93-99
by Abde Ali Kagalwalla, Puneet Gupta, Chris Progler, Steve McDonald
SMATO: Simultaneous mask and target optimization for improving lithographic process windowFull-text access may be available. Sign in or learn about subscription options.pp. 100-106
by Shayak Banerjee, Kanak B. Agarwal, Michael Orshansky
Template-mask design methodology for double patterning technologyFull-text access may be available. Sign in or learn about subscription options.pp. 107-111
by Chin-Hsiung Hsu, Yao-Wen Chang, Sani Richard Nassif
Fast and lossless graph division method for layout decomposition using SPQR-treeFull-text access may be available. Sign in or learn about subscription options.pp. 112-115
by Wai-Shing Luk, Huiping Huang
Design dependent process monitoring for back-end manufacturing cost reductionFull-text access may be available. Sign in or learn about subscription options.pp. 116-122
by Tuck-Boon Chan, Aashish Pant, Lerong Cheng, Puneet Gupta
SETS: Stochastic execution time scheduling for multicore systems by joint state space and Monte CarloFull-text access may be available. Sign in or learn about subscription options.pp. 123-130
by Nabeel Iqbal, Jörg Henkel
Combining optimistic and pessimistic DVS scheduling: An adaptive scheme and analysisFull-text access may be available. Sign in or learn about subscription options.pp. 131-138
by Simon Perathoner, Kai Lampka, Nikolay Stoimenov, Lothar Thiele, Jian-Jia Chen
Unified theory of real-time task scheduling and dynamic voltage/frequency Scaling on MPSoCsFull-text access may be available. Sign in or learn about subscription options.pp. 139-142
by Hessam Kooti, Eli Bozorgzadeh
In-place decomposition for robustness in FPGAFull-text access may be available. Sign in or learn about subscription options.pp. 143-148
by Ju-Yueh Lee, Zhe Feng, Lei He
MVP: Capture-power reduction with minimum-violations partitioning for delay testingFull-text access may be available. Sign in or learn about subscription options.pp. 149-154
by Zhen Chen, Krishnendu Chakrabarty, Dong Xiang
Testing methods for detecting stuck-open power switches in coarse-grain MTCMOS designsFull-text access may be available. Sign in or learn about subscription options.pp. 155-161
by Szu-Pang Mu, Yi-Ming Wang, Hao-Yu Yang, Mango C.-T. Chao, Shi-Hao Chen, Chih-Mou Tseng, Tsung-Ying Tsai
A scalable quantitative measure of IR-drop effects for scan pattern generationFull-text access may be available. Sign in or learn about subscription options.pp. 162-167
by M.-F. Wu, Kun-Han Tsai, Wu-Tung Cheng, H.-C. Pan, Jiun-Lang Huang, Augusli Kifli
Trace signal selection to enhance timing and logic visibility in post-silicon validationFull-text access may be available. Sign in or learn about subscription options.pp. 168-172
by Hamid Shojaei, Azadeh Davoodi
System-level impact of chip-level failure mechanisms and screensFull-text access may be available. Sign in or learn about subscription options.pp. 173-176
by Anne Gattiker
Cross-layer error resilience for robust systemsFull-text access may be available. Sign in or learn about subscription options.pp. 177-180
by Larkhoon Leem, Hyungmin Cho, Hsiao-Heng Lee, Young Moon Kim, Yanjing Li, Subhasish Mitra
Reliability, thermal, and power modeling and optimizationFull-text access may be available. Sign in or learn about subscription options.pp. 181-184
by Robert P. Dick
Symbolic system level reliability analysisFull-text access may be available. Sign in or learn about subscription options.pp. 185-189
by Michael Glaß, Martin Lukasiewycz, Felix Reimann, Christian Haubelt, Jürgen Teich
Hierarchical memory scheduling for multimedia MPSoCsFull-text access may be available. Sign in or learn about subscription options.pp. 190-196
by Ye-Jyun Lin, Chia-Lin Yang, Tay-Jyi Lin, Jiao-Wei Huang, Naehyuck Chang
Credit Borrow and Repay: Sharing DRAM with minimum latency and bandwidth guaranteesFull-text access may be available. Sign in or learn about subscription options.pp. 197-204
by Zefu Dai, Mark Jarvin, Jianwen Zhu
Scheduling of synchronous data flow models on scratchpad memory based embedded processorsFull-text access may be available. Sign in or learn about subscription options.pp. 205-212
by Weijia Che, Karam S. Chatha
The fast optimal voltage partitioning algorithm for peak power density minimizationFull-text access may be available. Sign in or learn about subscription options.pp. 213-217
by Jia Wang, Shiyan Hu
Post-placement power optimization with multi-bit flip-flopsFull-text access may be available. Sign in or learn about subscription options.pp. 218-223
by Yao-Tsung Chang, Chih-Cheng Hsu, Mark Po-Hung Lin, Yu-Wen Tsai, Sheng-Fong Chen
On power and fault-tolerance optimization in FPGA physical synthesisFull-text access may be available. Sign in or learn about subscription options.pp. 224-229
by Manu Jose, Yu Hu, Rupak Majumdar
Yield enhancement for 3D-stacked memory by redundancy sharing across diesFull-text access may be available. Sign in or learn about subscription options.pp. 230-234
by Li Jiang, Rong Ye, Qiang Xu
Mathematical yield estimation for two-dimensional-redundancy memory arraysFull-text access may be available. Sign in or learn about subscription options.pp. 235-240
by Mango C.-T. Chao, Ching-Yu Chin, Chen-Wei Lin
Analog test metrics estimates with PPM accuracyFull-text access may be available. Sign in or learn about subscription options.pp. 241-247
by Haralampos-G. Stratigopoulos, Salvador Mir
Design automation towards reliable analog integrated circuitsFull-text access may be available. Sign in or learn about subscription options.pp. 248-251
by Georges Gielen, Elie Maricau, Pieter De Wit
Digitalization of mixed-signal functionality in nanometer technologiesFull-text access may be available. Sign in or learn about subscription options.pp. 252-255
by Stephan Henzler
Efficient trace-driven metaheuristics for optimization of networks-on-chip configurationsFull-text access may be available. Sign in or learn about subscription options.pp. 256-263
by Andrew B. Kahng, Bill Lin, Kambiz Samadi, Rohit Sunkam Ramanujam
A self-evolving design methodology for power efficient multi-core systemsFull-text access may be available. Sign in or learn about subscription options.pp. 264-268
by Jin Sun, Rui Zheng, Jyothi Velamala, Yu Cao, Roman Lysecky, Karthik Shankar, Janet Roveda
An energy and power-aware approach to high-level synthesis of asynchronous systemsFull-text access may be available. Sign in or learn about subscription options.pp. 269-276
by John Hansen, Montek Singh
Clustering-based simultaneous task and voltage scheduling for NoC systemsFull-text access may be available. Sign in or learn about subscription options.pp. 277-283
by Yifang Liu, Yu Yang, Jiang Hu
Generalized nonlinear timing/phase macromodeling: Theory, numerical methods and applicationsFull-text access may be available. Sign in or learn about subscription options.pp. 284-291
by Chenjie Gu, Jaijeet Roychowdhury
Phase equations for quasi-periodic oscillatorsFull-text access may be available. Sign in or learn about subscription options.pp. 292-297
by Alper Demirt, Chenjie Gu, Jaijeet Roychowdhury
On-the-fly runtime adaptation for efficient execution of parallel multi-algorithm circuit simulationFull-text access may be available. Sign in or learn about subscription options.pp. 298-304
by Xiaoji Ye, Peng Li
An auction based pre-processing technique to determine detour in global routingFull-text access may be available. Sign in or learn about subscription options.pp. 305-311
by Yue Xu, Chris Chu
Simultaneous antenna avoidance and via optimization in layer assignment of multi-layer global routingFull-text access may be available. Sign in or learn about subscription options.pp. 312-318
by Tsung-Hsien Lee, Ting-Chi Wang
GLADE: A modern global router considering layer directivesFull-text access may be available. Sign in or learn about subscription options.pp. 319-323
by Yen-Jung Chang, Tsung-Hsien Lee, Ting-Chi Wang
Transaction level modeling in practice: Motivation and introductionFull-text access may be available. Sign in or learn about subscription options.pp. 324-331
by Guido Stehr, Josef Eckmu¨ller
Standards for System Level DesignFull-text access may be available. Sign in or learn about subscription options.pp. 332-335
by Laurent Maillet-Contoz
Design space exploration and performance evaluation at Electronic System Level for NoC-based MPSoCFull-text access may be available. Sign in or learn about subscription options.pp. 336-339
by Sören Sonntag, Francisco Gilabert
ESL solutions for low power designFull-text access may be available. Sign in or learn about subscription options.pp. 340-343
by Sylvian Kaiser, Ilija Materic, Rabih Saade
HW/SW co-design of parallel systemsFull-text access may be available. Sign in or learn about subscription options.pp. 344-348
by Enno Wein
Application specific processor design: Architectures, design methods and toolsFull-text access may be available. Sign in or learn about subscription options.pp. 349-352
by Achim Nohl, Frank Schirrmeister, Drew Taussig
Selective instruction set muting for energy-aware adaptive processorsFull-text access may be available. Sign in or learn about subscription options.pp. 353-360
by Muhammad Shafique, Lars Bauer, Jörg Henkel
Optimal algorithm for profile-based power gating: A compiler technique for reducing leakage on execution units in microprocessorsFull-text access may be available. Sign in or learn about subscription options.pp. 361-364
by Danbee Park, Jungseob Lee, Nam Sung Kim, Taewhan Kim
Memory access aware on-line voltage control for performance and energy optimizationFull-text access may be available. Sign in or learn about subscription options.pp. 365-372
by Xi Chen, Chi Xu, Robert P. Dick
SPIRE: A retiming-based physical-synthesis transformation systemFull-text access may be available. Sign in or learn about subscription options.pp. 373-380
by David A. Papa, Smita Krishnaswamy, Igor L. Markov
Redundant-wires-aware ECO timing and mask cost optimizationFull-text access may be available. Sign in or learn about subscription options.pp. 381-386
by Shao-Yun Fang, Tzuo-Fan Chien, Yao-Wen Chang
Through-silicon-via management during 3D physical design: When to add and how many?Full-text access may be available. Sign in or learn about subscription options.pp. 387-394
by Mohit Pathak, Young-Joon Lee, Thomas Moon, Sung Kyu Lim
Board driven I/O planning & optimizationFull-text access may be available. Sign in or learn about subscription options.pp. 395-397
by John F. Park
Recent research development in PCB layoutFull-text access may be available. Sign in or learn about subscription options.pp. 398-403
by Tan Yan, Martin D. F. Wong
Recent research development in flip-chip routingFull-text access may be available. Sign in or learn about subscription options.pp. 404-410
by Hsu-Chieh Lee, Yao-Wen Chang, Po-Wei Lee
Modeling and design for beyond-the-die power integrityFull-text access may be available. Sign in or learn about subscription options.pp. 411-416
by Yiyu Shi, Lei He
A synthesis flow for digital signal processing with biomolecular reactionsFull-text access may be available. Sign in or learn about subscription options.pp. 417-424
by Hua Jiang, Aleksandra P. Kharam, Marc D. Riedel, Keshab K. Parhi
A network-flow based pin-count aware routing algorithm for broadcast electrode-addressing EWOD chipsFull-text access may be available. Sign in or learn about subscription options.pp. 425-431
by Tsung-Wei Huang, Shih-Yuan Yeh, Tsung-Yi Ho
Variation tolerant sensing scheme of Spin-Transfer Torque Memory for yield improvementFull-text access may be available. Sign in or learn about subscription options.pp. 432-437
by Zhenyu Sun, Hai Li, Yiran Chen, Xiaobin Wang
Novel binary linear programming for high performance clock mesh synthesisFull-text access may be available. Sign in or learn about subscription options.pp. 438-443
by Minsik Cho, David Z. Pan, Ruchir Puri
Low-power clock trees for CPUsFull-text access may be available. Sign in or learn about subscription options.pp. 444-451
by Dong-Jin Lee, Myung-Chul Kim, Igor L. Markov
High variation-tolerant obstacle-avoiding clock mesh synthesis with symmetrical driving treesFull-text access may be available. Sign in or learn about subscription options.pp. 452-457
by Xin-Wei Shih, Hsu-Chieh Lee, Kuan-Hsien Ho, Yao-Wen Chang
Local clock skew minimization using blockage-aware mixed tree-mesh clock networkFull-text access may be available. Sign in or learn about subscription options.pp. 458-462
by Linfu Xiao, Zigang Xiao, Zaichen Qian, Yan Jiang, Tao Huang, Haitong Tian, Evangeline F. Y. Young
3D-ICE: Fast compact transient thermal modeling for 3D ICs with inter-tier liquid coolingFull-text access may be available. Sign in or learn about subscription options.pp. 463-470
by Arvind Sridhar, Alessandro Vincenzi, Martino Ruggiero, Thomas Brunschwiler, David Atienza
Cost-effective integration of three-dimensional (3D) ICs emphasizing testing cost analysisFull-text access may be available. Sign in or learn about subscription options.pp. 471-476
by Yibo Chen, Dimin Niu, Yuan Xie, Krishnendu Chakrabarty
Evaluation of using inductive/capacitive-coupling vertical interconnects in 3D network-on-chipFull-text access may be available. Sign in or learn about subscription options.pp. 477-482
by Jin Ouyang, Jing Xie, Matthew Poremba, Yuan Xie
Scalable segmentation-based malicious circuitry detection and diagnosisFull-text access may be available. Sign in or learn about subscription options.pp. 483-486
by Sheng Wei, Miodrag Potkonjak
Application-Aware diagnosis of runtime hardware faultsFull-text access may be available. Sign in or learn about subscription options.pp. 487-492
by Andrea Pellegrini, Valeria Bertacco
Manufacturing and characteristics of low-voltage organic thin-film transistorsFull-text access may be available. Sign in or learn about subscription options.pp. 493-495
by Hagen Klauk, Ute Zschieschang
Design and manufacturing of organic RFID circuits: Coping with intrinsic parameter variations in organic devices by circuit designFull-text access may be available. Sign in or learn about subscription options.pp. 496-499
by Jan Genoe, Kris Myny, Soeren Steudel, Paul Heremans
Design of large area electronics with organic transistorsFull-text access may be available. Sign in or learn about subscription options.pp. 500-503
by Makoto Takamiya, Koichi Ishida, Tsuyoshi Sekitani, Takao Someya, Takayasu Sakurai
Design of analog circuits using organic field-effect transistorsFull-text access may be available. Sign in or learn about subscription options.pp. 504-507
by Boris Murmann, Wei Xiong
Active learning framework for post-silicon variation extraction and test cost reductionFull-text access may be available. Sign in or learn about subscription options.pp. 508-515
by Cheng Zhuo, Kanak Agarwal, David Blaauw, Dennis Sylvester
Analysis of circuit dynamic behavior with timed ternary decision diagramFull-text access may be available. Sign in or learn about subscription options.pp. 516-523
by Lu Wan, Deming Chen
Fast statistical timing analysis of latch-controlled circuits for arbitrary clock periodsFull-text access may be available. Sign in or learn about subscription options.pp. 524-531
by Bing Li, Ning Chen, Ulf Schlichtmann
On timing-independent false path identificationFull-text access may be available. Sign in or learn about subscription options.pp. 532-535
by Feng Yuan, Qiang Xu
3POr — Parallel projection based parameterized order reduction for multi-dimensional linear modelsFull-text access may be available. Sign in or learn about subscription options.pp. 536-542
by Jorge Fernández Villena, Luís Miguel Silveira
A hierarchical matrix inversion algorithm for vectorless power grid verificationFull-text access may be available. Sign in or learn about subscription options.pp. 543-550
by Xuanxing Xiong, Jia Wang
Fast thermal analysis on GPU for 3D-ICs with integrated microchannel coolingFull-text access may be available. Sign in or learn about subscription options.pp. 551-555
by Zhuo Feng, Peng Li
Native-conflict-aware wire perturbation for double patterning technologyFull-text access may be available. Sign in or learn about subscription options.pp. 556-561
by Szu-Yu Chen, Yao-Wen Chang
A lower bound computation method for evaluation of statistical design techniquesFull-text access may be available. Sign in or learn about subscription options.pp. 562-569
by Vineeth Veetil, Dennis Sylvester, David Blaauw
Timing yield optimization via discrete gate sizing using globally-informed delay PDFsFull-text access may be available. Sign in or learn about subscription options.pp. 570-577
by Shantanu Dutt, Huan Ren
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