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Proceedings 1994 IEEE International Conference on Computer Design: VLSI in Computers and Processors

Oct. 10 1994 to Oct. 12 1994

Cambridge, MA, USA

Table of Contents

Proceedings 1994 IEEE International Conference on Computer Design: VLSI in Computers and ProcessorsFreely available from IEEE.pp. 0_1-0_1
OK, if these CAD tools are so great, why isn't my chip design on schedule?Full-text access may be available. Sign in or learn about subscription options.pp. 3
by N. Weste
The future of programmable logic and its impact on digital system designFull-text access may be available. Sign in or learn about subscription options.pp. 10,11,12,13,14,15,16
by W.S. Carter
Emerging technologies for electronic design and testFull-text access may be available. Sign in or learn about subscription options.pp. 18
by P. Agrawal
Grammar-based optimization of synthesis scenariosFull-text access may be available. Sign in or learn about subscription options.pp. 20,21,22,23,24,25
by A. Kuehlmann, L.P.P.P. Van Ginneken
Architecture oriented logic optimization for lookup table based FPGAsFull-text access may be available. Sign in or learn about subscription options.pp. 26,27,28,29
by A. Lu, J. Saul, E. Dagless
FPGA synthesis using function decompositionFull-text access may be available. Sign in or learn about subscription options.pp. 30,31,32,33,34,35
by Y.-T. Lai, K.-R. Ricky Pan, M. Pedram
Efficient Boolean matching algorithm for cell librariesFull-text access may be available. Sign in or learn about subscription options.pp. 36,37,38,39
by Q. Wu, C.Y.R. Chen, J.M. Acken
A superassociative tagged cache coherence directoryFull-text access may be available. Sign in or learn about subscription options.pp. 42,43,44,45
by D.J. Lilja, S. Ambalavanan
Issues in multi-level cache designsFull-text access may be available. Sign in or learn about subscription options.pp. 46,47,48,49,50,51,52
by L. Liu
Analysis of multiprocessor memory reference behaviorFull-text access may be available. Sign in or learn about subscription options.pp. 53,54,55,56,57,58,59
by J.D. Gee, A.J. Smith
Determination of optimal sizes for a first and second level SRAM-DRAM on-chip cache combinationFull-text access may be available. Sign in or learn about subscription options.pp. 60,61,62,63,64
by R. Hundal, V.G. Oklobdzija
Design and evaluation of the high performance multi-processor serverFull-text access may be available. Sign in or learn about subscription options.pp. 66,67,68,69
by M. Morioka, K. Kurosawa, S. Miura, T. Nakamikawa, S. Ishikawa
A massively parallel multithreaded architecture: DAVRIDFull-text access may be available. Sign in or learn about subscription options.pp. 70,71,72,73,74
by Sangho Ha, Junghwan Kim, Eunha Rho, Yoonhee Nah, Sangyong Han, Daejoon Hwang, Heunghwan Kim, Seungho Cho
Distributed reconfiguration of fault tolerant VLSI multipipeline arrays with constant interstage path lengthsFull-text access may be available. Sign in or learn about subscription options.pp. 75,76,77,78
by H. Al-Asaad, M. Vai, J. Feldman
Fault tolerant processor arrays for nonlinear shortest path problemFull-text access may be available. Sign in or learn about subscription options.pp. 79,80,81,82,83
by C.G. Oh, H.Y. Youn
Delay-verifiability of combinational circuits based on primitive faultsFull-text access may be available. Sign in or learn about subscription options.pp. 86,87,88,89,90
by W. Ke, P.R. Menon
Behavioral synthesis for hierarchical testability of controller/data path circuits with conditional branchesFull-text access may be available. Sign in or learn about subscription options.pp. 91,92,93,94,95,96
by S. Bhatia, N.K. Jha
Testability considerationsFull-text access may be available. Sign in or learn about subscription options.pp. 97,98,99,100
by S.-Z. Sun, D.H.C. Du, D.-R. Liu
SYNCBIST: SYNthesis for concurrent built-in self-testabilityFull-text access may be available. Sign in or learn about subscription options.pp. 101,102,103,104
by I.G. Harris, A. Orailoglu
OFDD based minimization of fixed polarity Reed-Muller expressions using hybrid genetic algorithmsFull-text access may be available. Sign in or learn about subscription options.pp. 106,107,108,109,110
by B. Becker, R. Drechsler
Tradeoffs in canonical sequential function representationsFull-text access may be available. Sign in or learn about subscription options.pp. 111,112,113,114,115,116
by A. Gupta, A.L. Fisher
Capturing synchronization specifications for sequential compositionsFull-text access may be available. Sign in or learn about subscription options.pp. 117,118,119,120,121
by Z. Zhu, S.D. Johnson
Concurrent error detection in high speed carry-free division using alternative input dataFull-text access may be available. Sign in or learn about subscription options.pp. 124,125,126,127
by C.-L. Wey
Design of TSC code-disjoint inverter-free PLA's for separable unordered codesFull-text access may be available. Sign in or learn about subscription options.pp. 128,129,130,131
by S.J. Piestrak
On-chip TEC-QED ECC for ultra-large, single-chip memory systemsFull-text access may be available. Sign in or learn about subscription options.pp. 132,133,134,135,136,137
by F. Alzahrani, T. Chen
Dynamic list-scheduling with finite resourcesFull-text access may be available. Sign in or learn about subscription options.pp. 140,141,142,143,144
by R.A. Kamin, G.B. Adams, P.K. Dubey
PRISC software acceleration techniquesFull-text access may be available. Sign in or learn about subscription options.pp. 145,146,147,148,149
by R. Razdan, K. Brace, M.D. Smith
Communication sensitive rotation schedulingFull-text access may be available. Sign in or learn about subscription options.pp. 150,151,152,153
by S. Tongsima, N.L. Passos, E.H.-M. Sha
Efficient timing analysis for CMOS circuit considering data dependent delaysFull-text access may be available. Sign in or learn about subscription options.pp. 156,157,158,159
by S.-Z. Sun, D.H.C. Du, H.-C. Chen
Short destabilizing paths in timing verificationFull-text access may be available. Sign in or learn about subscription options.pp. 160,161,162,163
by R.P. Llopis, L.R. Xirgo, J.C. Bordoll
Synchronization of wave-pipelined circuitsFull-text access may be available. Sign in or learn about subscription options.pp. 164,165,166,167
by X. Zhang, R. Sridhar
Mesh routing topologies for multi-FPGA systemsFull-text access may be available. Sign in or learn about subscription options.pp. 170,171,172,173,174,175,176,177
by S. Hauck, G. Borriello, C. Ebeling
PROTEUS: programmable hardware for telecommunication systemsFull-text access may be available. Sign in or learn about subscription options.pp. 178,179,180,181,182,183
by N. Ohta, H. Nakada, K. Yamada, A. Tsutsui, T. Miyazaki
Area and time limitations of FPGA-based virtual hardwareFull-text access may be available. Sign in or learn about subscription options.pp. 184,185,186,187,188,189
by O.T. Albaharna, P.Y.K. Cheung, T.J. Clarke
AS/400 64-bit powerPC-compatible processor implementationFull-text access may be available. Sign in or learn about subscription options.pp. 192,193,194,195,196
by J.M. Borkenhagen, G.H. Handlogten, J.D. Irish, S.B. Levenstein
AS/400 PowerPC compatible semi-custom technologyFull-text access may be available. Sign in or learn about subscription options.pp. 197,198,199,200,201,202
by M. Gruver, N. Phan, T. Aipperspach, S. Hilker, J. Bartley
A 32-bit superscalar microprocessor with 64-bit processing and high bandwidth DRAM interfaceFull-text access may be available. Sign in or learn about subscription options.pp. 203,204,205,206,207,208,209,210
by M. Matsuo, H. Kondo, Y. Takata, S. Kobayashi, M. Satoh, T. Yoshida, Y. Saito, J.-I. Hinata
Area efficient synthesis of asynchronous interface circuitsFull-text access may be available. Sign in or learn about subscription options.pp. 212,213,214,215,216
by R. Puri, J. Gu
The design and evaluation of an asynchronous microprocessorFull-text access may be available. Sign in or learn about subscription options.pp. 217,218,219,220
by S.B. Furber, P. Day, J.D. Garside, N.C. Paver, S. Temple, J.V. Woods
Performance analysis and optimization of asynchronous circuitsFull-text access may be available. Sign in or learn about subscription options.pp. 221,222,223,224
by P. Kudva, G. Gopalakrishnan, E. Brunvand, V. Akella
Automatic verification of refinementFull-text access may be available. Sign in or learn about subscription options.pp. 226,227,228,229
by Wing Sang Lee, M.R. Greenstreet, C.-J. Seger
Efficient state space pruning in symbolic backward traversalFull-text access may be available. Sign in or learn about subscription options.pp. 230,231,232,233,234,235
by G. Cabodi, P. Camurati, S. Quer
A structural approach to state space decomposition for approximate reachability analysisFull-text access may be available. Sign in or learn about subscription options.pp. 236,237,238,239
by Hyunwoo Cho, G.D. Hachtel, E. Macii, M. Poncino, F. Somenzi
An exact optimization of two-level acyclic sequential circuitsFull-text access may be available. Sign in or learn about subscription options.pp. 242,243,244,245,246,247,248,249
by E.M. Sentovich, R.K. Brayton
State assignment for power and area minimizationFull-text access may be available. Sign in or learn about subscription options.pp. 250,251,252,253,254
by Kuo-Hua Wang, Wen-Sing Wang, T.T. Hwang, A.C.H. Wu, Youn-Long Lin
Minimizing interacting finite state machines: a compositional approach to language containmentFull-text access may be available. Sign in or learn about subscription options.pp. 255,256,257,258,259,260,261
by A. Aziz, V. Singhal, R. Brayton, G.M. Swamy
Continuations in hardware-software codesignFull-text access may be available. Sign in or learn about subscription options.pp. 264,265,266,267,268,269
by M.E. Tuna, S.D. Johnson, R.G. Burger
Compression of embedded system programsFull-text access may be available. Sign in or learn about subscription options.pp. 270,271,272,273,274,275,276,277
by M. Kozuch, A. Wolfe
HW/SW codesign for embedded telecom systemsFull-text access may be available. Sign in or learn about subscription options.pp. 278,279,280,281
by S. Antoniazzi, A. Balboni, W. Fornaciari, D. Sciuto
A signature analyzer for analog and mixed-signal circuitsFull-text access may be available. Sign in or learn about subscription options.pp. 284,285,286,287
by N. Nagi, A. Chatterjee, J.A. Abraham
WRAPTure: a tool for evaluation and optimization of weights for weighted random pattern testingFull-text access may be available. Sign in or learn about subscription options.pp. 288,289,290
by A. Majumdar
A class of good characteristic polynomials for LFSR test pattern generatorsFull-text access may be available. Sign in or learn about subscription options.pp. 292,293,294,295
by D. Kagaris, S. Tragoudas
A parallel CMOS 2's complement multiplier based on 5:3 counterFull-text access may be available. Sign in or learn about subscription options.pp. 298,299,300,301
by Z. Guan, P. Thomson, A.E.A. Almaini
A new asynchronous multiplier using Enable/Disable CMOS Differential LogicFull-text access may be available. Sign in or learn about subscription options.pp. 302,303,304,305
by E. de Angel, E. Swartzlander, J. Abraham
An arbitration tree adapted to object oriented associative memoriesFull-text access may be available. Sign in or learn about subscription options.pp. 306,307,308,309,310
by D. Archambaud, P. Faudemay
Write buffer design for on-chip cacheFull-text access may be available. Sign in or learn about subscription options.pp. 311,312,313,314,315,316
by P.P. Chu, R. Gottipati
Behavioral synthesis for low powerFull-text access may be available. Sign in or learn about subscription options.pp. 318,319,320,321,322
by A. Raghunathan, N.K. Jha
Microarchitectural synthesis of performance-constrained, low-power VLSI designsFull-text access may be available. Sign in or learn about subscription options.pp. 323,324,325,326
by L. Goodby, A. Orailoglu, P.M. Chau
Allocation and binding during fault-secure microarchitecture synthesisFull-text access may be available. Sign in or learn about subscription options.pp. 327,328,329,330
by S. Sokolov, R. Karri
Integrating binding constraints in the synthesis of area-efficient self-recovering microarchitecturesFull-text access may be available. Sign in or learn about subscription options.pp. 331,332,333,334
by K. Hogstedt, A. Orailoglu
POWER2 architecture and performanceFull-text access may be available. Sign in or learn about subscription options.pp. 336,337,338,339
by E.L. Hannon, F.P. O'Connell, L.J. Shieh
The effects of compiler options on application performanceFull-text access may be available. Sign in or learn about subscription options.pp. 340,341,342,343
by K.E. Stewart, S.W. White
Architectural performance verification: PowerPC processorsFull-text access may be available. Sign in or learn about subscription options.pp. 344,345,346,347
by S. Surya, P. Bose, J.A. Abraham
Testability analysis for test generation in synchronous sequential circuitsFull-text access may be available. Sign in or learn about subscription options.pp. 350,351,352,353
by R. Wolber, U. Glaser, H.T. Vierhaus
A new test generation methodology using selective clocking for the clock line controlled circuitsFull-text access may be available. Sign in or learn about subscription options.pp. 354,355,356,357,358
by Sanghyeon Baeg, W.A. Rogers
Path-delay fault simulation for a standard scan design methodologyFull-text access may be available. Sign in or learn about subscription options.pp. 359-362
by Sungho Kang, Wai-On Law, B. Underwood
Multifault testable circuits based on binary parity diagramsFull-text access may be available. Sign in or learn about subscription options.pp. 363,364,365,366
by S. Kundu
Timing verification and optimization for the PowerPC processor familyFull-text access may be available. Sign in or learn about subscription options.pp. 390,391,392,393
by R.E. Mains, T.A. Mosher, L.P.P.P. van Ginneken, R.F. Damiano
Two-phase logic design by hardware flowchartsFull-text access may be available. Sign in or learn about subscription options.pp. 368,369,370,371,372,373,374,375,376,377,378,379,380
by K. Covey, S. Murdock, T. Shiple
On valid clocking for combinational circuitsFull-text access may be available. Sign in or learn about subscription options.pp. 381,382,383,384
by Shang-Zhi Sun, D.H.C. Du, Yaun-Chung Hsu, Hsi-Chuan Chen
Latch design for transient pulse toleranceFull-text access may be available. Sign in or learn about subscription options.pp. 385,386,387,388
by Hungse Cha, J.H. Patel
On retiming for FPGA logic module minimizationFull-text access may be available. Sign in or learn about subscription options.pp. 394,395,396,397
by Y.P. Chen, D.F. Wong
Retiming for the global optimization of synchronous sequential circuitFull-text access may be available. Sign in or learn about subscription options.pp. 398,399,400,401
by S. Lejmi, B. Kaminska, E. Wagneur
The PowerPC 604 microprocessor design methodologyFull-text access may be available. Sign in or learn about subscription options.pp. 404,405,406,407,408
by C. Roth, R. Lewelling, T. Brodnax
Single chip PCI bridge and memory controller for PowerPC microprocessorsFull-text access may be available. Sign in or learn about subscription options.pp. 409,410,411,412
by M.J. Garcia, B.K. Reynolds
PowerPC visual simulator: peeking under the hood of the PowerPC engineFull-text access may be available. Sign in or learn about subscription options.pp. 413,414,415,416,417,418
by M. Armstead, M. Cogswell, S. Halverson, T. Musta
Fourier transform based DS/FH spread spectrum receiverFull-text access may be available. Sign in or learn about subscription options.pp. 420,421,422,423
by J.P.F. Glas, S.E. Skolnik
An FPGA based configurable I/O system for AC drive controllersFull-text access may be available. Sign in or learn about subscription options.pp. 424,425,426,427
by D.R. Woodward, D.C. Levy, R.G. Harley
Design of an embedded video compression system-a quantitative approachFull-text access may be available. Sign in or learn about subscription options.pp. 428,429,430,431
by J. Wilberg, R. Camposano, U. Westerholz, U. Steinhausen
UCLOCK: automated design of high-performance unclocked state machinesFull-text access may be available. Sign in or learn about subscription options.pp. 434,435,436,437,438,439,440,441
by S.M. Nowick, B. Coates
Peephole optimization of asynchronous macromodule networksFull-text access may be available. Sign in or learn about subscription options.pp. 442,443,444,445,446
by G.C. Gopalakrishnan, P.N. Kudva, E.L. Brunvand
Initialization issues in the synthesis of asynchronous circuitsFull-text access may be available. Sign in or learn about subscription options.pp. 447,448,449,450,451,452
by S. Banerjee, R.K. Roy, S.T. Chakradhar, D.K. Pradhan
Architectural verification of processors using symbolic instruction graphsFull-text access may be available. Sign in or learn about subscription options.pp. 454,455,456,457,458,459
by A.K. Chandra, V.S. Iyengar, R.V. Jawalekar, M.P. Mullen, I. Nair, B.K. Rosen
A parallel method for functional verification of medium and high throughput DSP synthesisFull-text access may be available. Sign in or learn about subscription options.pp. 460,461,462,463
by M. Genoe, L. Claesen, H. De Man
The structured logic CAD suite used on the DPS7000 systemFull-text access may be available. Sign in or learn about subscription options.pp. 464,465,466,467
by H.N. Nguyen, J.P. Tual, L. Ducousso, M. Thill, P. Vallet
Optimal logic blocks for FPGAs, using factorial design techniquesFull-text access may be available. Sign in or learn about subscription options.pp. 470,471,472,473,474
by F. Haq, S. Mourad
Routing architectures for hierarchical field programmable gate arraysFull-text access may be available. Sign in or learn about subscription options.pp. 475,476,477,478
by A.A. Aggarwal, D.M. Lewis
Defect tolerant SRAM based FPGAsFull-text access may be available. Sign in or learn about subscription options.pp. 479,480,481,482
by J.L. Kelly, P.A. Ivey
Domain based testing: increasing test case reuseFull-text access may be available. Sign in or learn about subscription options.pp. 484,485,486,487,488,489,490,491
by A. von Mayrhauser, R. Mraz, J. Walls, P. Ocken
Software metrics for object-oriented designsFull-text access may be available. Sign in or learn about subscription options.pp. 492,493,494,495
by R.V. Hudli, C.L. Hoskins, A.V. Hudli
Combinational digit-set converters for hybrid radix-4 arithmeticFull-text access may be available. Sign in or learn about subscription options.pp. 498,499,500,501,502,503
by L. Montalvo, A. Guyot
A self-timed divider using RSD number systemFull-text access may be available. Sign in or learn about subscription options.pp. 504,505,506,507
by Kiyoung Choi, KiJong Lee, Jun-Woo Kang
Design of high-speed residue-to-binary number system converter based on Chinese Remainder TheoremFull-text access may be available. Sign in or learn about subscription options.pp. 508,509,510,511
by S.J. Piestrak
Complex operator synthesisFull-text access may be available. Sign in or learn about subscription options.pp. 514,515,516,517
by M. Quayle, Chi-Lai Huang
In the driver's seat of BooleDozerFull-text access may be available. Sign in or learn about subscription options.pp. 518,519,520,521
by D. Brand, R.F. Damiano, L.P.P.P. van Ginneken, A.D. Drumm
ASOP: arithmetic sum-of-products generatorFull-text access may be available. Sign in or learn about subscription options.pp. 522,523,524,525,526
by D. Kumar, B. Erickson
ZEPHCAD and FLORA: logic synthesis for control and datapathFull-text access may be available. Sign in or learn about subscription options.pp. 527,528,529,530
by H. Sato, M. Yamazaki, M. Fujita
Future needs for automotive electronicsFull-text access may be available. Sign in or learn about subscription options.pp. 532,533,534,535,536,537,538,539
by P. Thoma
A VLSI chip for template matchingFull-text access may be available. Sign in or learn about subscription options.pp. 542,543,544,545
by N. Ranganathan, S. Venugopal
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