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2024 IEEE 42nd International Conference on Computer Design (ICCD)

Nov. 18 2024 to Nov. 20 2024

Milan, Italy

ISBN: 979-8-3503-8040-8

Table of Contents

pp. 1-1

pp. 1-1

pp. 1-1

Table of Contents

pp. v-xx

Message from the General Chair: ICCD 2024

pp. xxi-xxi

Message from the Program Chairs: ICCD 2024

pp. xxii-xxiii

Organizing Committee

pp. xxiv-xxiv

Program Committee

pp. xxv-xxx

pp. xxxi-xxxi

pp. 1-4

pp. xxxvi-xxxvi

ChaoSen: Security Enhancement of Image Sensor through in-Sensor Chaotic Computing

pp. 1-8

by Nedasadat Taheri, Sepehr Tabrizchi, Shaahin Angizi, Arman Roohi

Memristive Logic-in-Memory Implementation with Area Efficiency and Parallelism

pp. 9-15

by Ikkyum Kim, Heechun Park

S3M: Static Semi-Segmented Multipliers for Energy-Efficient DNN Inference Accelerators

pp. 16-23

by Mingtao Zhang, Quan Cheng, Hiromitsu Awano, Longyang Lin, Masanori Hashimoto

Optimizing Quantum Circuit Synthesis with Dominator Analysis

pp. 24-27

by Giacomo Lancellotti, Giovanni Agosta, Alessandro Barenghi, Gerardo Pelosi

MemSort: In-Memory Sorting Architecture

pp. 28-35

by Rui Liu, Xiaoyu Zhang, Xinyu Wang, Feng Min, Zhejian Luo, Xiaoming Chen, Yinhe Han, Minghua Tang

MuSA: Multi-Sketch Accelerator with Hybrid Parallelism and Coalesced Memory Organization

pp. 36-43

by Sunan Zou, Bizhao Shi, Ziyun Zhang, Guojie Luo

CoPIM: A Collaborative Scheduling Framework for Commodity Processing-in-memory Systems

pp. 44-51

by Shunchen Shi, Xueqi Li, Zhaowu Pan, Peiheng Zhang, Ninghui Sun

ChameSC: Virtualizing Superscalar Core of a SIMD Architecture for Vector Memory Access

pp. 52-59

by Zhongzhu Pu, Guangda Zhang, Tiejian Zhang, Chen Zhang, Youhui Zhang, Xia Zhao

Multi: Reduce Energy Overhead of Criticality-Aware Dynamic Instruction Scheduling for Energy Efficiency

pp. 60-67

by Honglan Zhan, Chenxi Wang, Xin Wang, Chun Yang, Xianhua Liu, Xu Cheng

T-BUS: Taming Bipartite Unstructured Sparsity for Energy-Efficient DNN Acceleration

pp. 68-75

by Ning Yang, Fangxin Liu, Zongwu Wang, Zhiyan Song, Tao Yang, Li Jiang

PS4: A Low Power SNN Accelerator with Spike Speculative Scheme

pp. 76-83

by Zongwu Wang, Fangxin Liu, Xin Tang, Li Jiang

PCCL: Energy-Efficient LLM Training with Power-Aware Collective Communication

pp. 84-91

by Ziyang Jia, Laxmi N. Bhuyan, Daniel Wong

Ensuring the Accuracy of CNN Accelerators Supplied at Ultra-Low Voltage

pp. 92-95

by Yamilka Toca-Díaz, Rubén Gran Tejero, Alejandro Valero

A Semi Black-Box Adversarial Bit- Flip Attack with Limited DNN Model Information

pp. 96-104

by Behnam Ghavami, Mani Sadati, Mohammad Shahidzadeh, Lesley Shannon, Steve Wilton

Blink: Breaking Parallel Implementation of Crystals-Kyber with Side-Channel Attack

pp. 105-113

by Jian Wang, Weiqiong Cao, Hua Chen, Haoyuan Li

Hound: Locating Cryptographic Primitives in Desynchronized Side-Channel Traces using Deep-Learning

pp. 114-121

by Davide Galli, Giuseppe Chiari, Davide Zoni

Interpretable Risk-aware Access Control for Spark: Blocking Attack Purpose Behind Actions

pp. 122-129

by Wenbo Wang, Tao Xue, Shuailou Li, Zhaoyang Wang, Boyang Zhang, Yu Wen

TDM: Time and Distance Metric for Quantifying Information Leakage Vulnerabilities in SoCs

pp. 130-133

by Avinash Ayalasomayajula, Henin Li, Hasan Al Shaikh, Sujan Kumar Saha, Farimah Farahmandi

Transformer-Characterized Approach for Chip Floorplanning: Leveraging HyperGCN and DTQN

pp. 134-143

by Wenbo Guan, Xiaoyan Tang, Hongliang Lu, Jingru Tan, Jinlong Wang, Yuming Zhang

Elastic EDA: Auto-Scaling Cloud Resources for EDA Tasks via Learning-based Approaches

pp. 144-153

by Linyu Zhu, Xingyu Ma, Shaogang Hao, Yushan Pan, Xinfei Guo

RNC: Efficient RRAM-aware NAS and Compilation for DNNs on Resource-Constrained Edge Devices

pp. 154-161

by Kam Chi Loong, Shihao Han, Sishuo Liu, Ning Lin, Zhongrui Wang

AutoVCoder: A Systematic Framework for Automated Verilog Code Generation using LLMs

pp. 162-169

by Mingzhe Gao, Jieru Zhao, Zhe Lin, Wenchao Ding, Xiaofeng Hou, Yu Feng, Chao Li, Minyi Guo

Reinforcement Learning-Driven Co-Scheduling and Diverse Resource Assignments on NUMA Systems

pp. 170-178

by Urvij Saroliya, Eishi Arima, Dai Liu, Martin Schulz

Rethinking High-Level Synthesis Design Space Exploration from a Contrastive Perspective

pp. 179-182

by Huiliang Hong, Chenglong Xiao, Shanshan Wang

ParaCkpt: Heterogeneous Multi-Path Checkpointing Mechanism for Training Deep Learning Models

pp. 183-190

by Shucheng Wang, Qiang Cao, Kaiye Zhou, Jun Xu, Zhandong Guo, Jiannan Guo

RTDeepEnsemble: Real-Time DNN Ensemble Method for Machine Perception Systems

pp. 191-198

by Zitong Bo, Chaoping Guo, Chang Leng, Ying Qiao, Hongan Wang

Interference-Aware DNN Serving on Heterogeneous Processors in Edge Systems

pp. 199-206

by Yeonjae Kim, Igjae Kim, Kwanghoon Choi, Jeongseob Ahn, Jongse Park, Jaehyuk Huh

HOLES: Boosting Large Language Models Efficiency with Hardware-Friendly Lossless Encoding

pp. 207-214

by Fangxin Liu, Ning Yang, Zhiyan Song, Zongwu Wang, Li Jiang

OLSATM: Online Learning Based State-Aware Task Migration on S-NUCA Many-Cores

pp. 215-218

by Yandong He, Guangda Zhang, Yongjun Zhang, Hengzhu Liu, Renzhi Chen

Co-Designing a 3D Transformation Accelerator for Versal-Based Image Registration

pp. 219-222

by Paolo Salvatore Galfano, Giuseppe Sorrentino, Eleonora D'Arnese, Davide Conficconi

Read-Optimized Persistent Hash Index for Query Acceleration through Fingerprint Filtering and Lock-Free Prefetching

pp. 223-230

by Renzhi Xiao, Dan Feng, Yuchong Hu, Hong Jiang, Lin Wang, Yucheng Zhang, Lanlan Cui, Guanglei Xu, Fang Wang

Optimizing Structural Modification Operation for B+-Tree on Byte-Addressable Devices

pp. 231-238

by Dingze Hong, Jinlei Hu, Jianxi Chen, Dan Feng, Jian Liu

FastMatch: Enhancing Data Pipeline Efficiency for Accelerated Distributed Training

pp. 239-246

by Jianchang Su, Masoud Rahimi Jafari, Yifan Zhang, Wei Zhang

Multi-Stage Dynamic Cuckoo Filters

pp. 247-255

by Jun Su, Yinjin Fu, Nong Xiao

Persistent Spiral Storage

pp. 256-259

by Wenyu Peng, Tao Xie, Paul H. Siegel

Advanced Dynamic Scalarisation for RISC-V GPGPUs

pp. 260-267

by Matthew Naylor, Alexandre Joannou, A. Theodore Markettos, Paul Metzger, Simon W. Moore, Timothy M. Jones

Extending RISC-V for Efficient Overflow Recovery in Mixed-Precision Computations

pp. 268-275

by Luca Bertaccini, Siyuan Shen, Torsten Hoefler, Luca Benini

Ventus: A High-performance Open-source GPGPU Based on RISC-V and Its Vector Extension

pp. 276-279

by Jingzhou Li, Kexiang Yang, Chufeng Jin, Xudong Liu, Zexia Yang, Fangfei Yu, Yujie Shi, Mingyuan Ma, Li Kong, Jing Zhou, Hualin Wu, Hu He

HeroSDK: Streamlining Heterogeneous RISC-V Accelerated Computing from Embedded to High-Performance Systems

pp. 280-287

by Cyril Koenig, Björn Forsberg, Luca Benini

vCLIC: Towards Fast Interrupt Handling in Virtualized RISC-V Mixed-Criticality Systems

pp. 288-291

by Enrico Zelioli, Alessandro Ottaviano, Robert Balas, Nils Wistoff, Angelo Garofalo, Luca Benini

PCC: An End-to-End Compilation Framework for Neural Networks on Photonic-Electronic Accelerators

pp. 292-299

by Bohan Hu, Yinyi Liu, Zhenguo Liu, Wei Zhang, Jiang Xu

Tango: Low Latency Multi-DNN Inference on Heterogeneous Edge Platforms

pp. 300-307

by Zain Taufique, Aman Vyas, Antonio Miele, Pasi Liljeberg, Anil Kanduri

Private Tensor Freezing for an Efficient Federated Learning with Homomorphic Encryption

pp. 308-315

by Valentino Peluso, Erich Malan, Andrea Calimera, Enrico Macii

Pseudo-Sim: An Accurate Analytical Modeling Framework for Systolic Array Architectures

pp. 316-319

by Dan Sturm, Sajjad Moazeni

Fine-Grained Shared Cache Interference Analysis Using Basic Block's Execution Time

pp. 320-323

by Yixuan Zhu, Wenqi Lou, Yinkang Gao, Binze Jiang, Xiaohang Gong, Xi Li

SchInFS: A File System Integrating Functions of the Block I/O Scheduler for ZNS SSDs

pp. 324-331

by Jintong Zhang, Haichuan Hu, Jianxi Chen, Yekang Zhan

GCC: Optimizing Space Efficiency and Read Latency of SSDs with Workload-Aware Garbage Collection Aided Compression

pp. 332-339

by Linhui Liu, Yunfei Gu, Chenhao Zhu, Chentao Wu, Jie Li, Minyi Guo

LBZ: A Lightweight Block Device for Supporting F2FS on ZNS SSD

pp. 340-347

by Yongpeng Yang, Dejun Jiang, Bo Jiang, Hao-Chiang Hsu, Liang Peng, Zifeng Yang

RAID45: Hybrid Parity-Based RAID for Reducing Parity Write Wear on High-Density SSDs

pp. 348-355

by Jialin Liu, Yujiong Liang, Yunpeng Song, Liang Shi

SmartNetSSD: Exploiting Path Resources for Read Performance Improvement in Network-Based SSDs

pp. 356-359

by Jinhua Cui, Feiyu Chen, Lu Li, Shiqiang Nie, Laurence T. Yang

SuperMap: High-Performance and Flexible Memory-Mapped IO for Fast Storage Device

pp. 360-363

by Wenqing Jia, Dejun Jiang, Jin Xiong

Safe Speculation for CHERI

pp. 364-372

by Franz A. Fuchs, Jonathan Woodruff, Peter Rugg, Alexandre Joannou, Jessica Clarke, John Baldwin, Brooks Davis, Peter G. Neumann, Robert N. M. Watson, Simon W. Moore

APE-FV: Concolic Testing for RTL Functional Verification Using Adaptive Path Exploration

pp. 373-380

by Ziyue Zheng, Xiangchen Meng, Yangdi Lyu

HAp-FT: A Hybrid Approximate Fault Tolerance Framework for DNN Accelerator

pp. 381-388

by Xiaohui Wei, Chenyang Wang, Zeyu Guan, Fengyi Li, Hengshan Yue

LLM - TG: Towards Automated Test Case Generation for Processors Using Large Language Models

pp. 389-396

by Yifei Deng, Renzhi Chen, Chao Xiao, Zhijie Yang, Yuanfeng Luo, Jingyue Zhao, Na Li, Zhong Wan, Yongbao Ai, Huadong Dai, Lei Wang

NexusCIM: High-Throughput Multi-CIM Array Architecture with C-Mesh NoC and Hub Cores

pp. 401-408

by Hyunmin Kim, Sungju Ryu

Dual-Axis ECC: Vertical and Horizontal Error Correction for Storage and Transfer Errors

pp. 409-417

by Giyong Jung, Hee Ju Na, Sang-Hyo Kim, Jungrae Kim

VarVE: Bringing SIMD Performance to Variable-Width Values

pp. 418-425

by Chen Zou, Andrew A. Chien

Ninja: A Hardware Assisted System for Accelerating Nested Address Translation

pp. 426-433

by Longyu Zhao, Zongwu Wang, Fangxin Liu, Li Jiang

HEncode: A Highly Modularized and Efficient FPGA QC-LDPC Encoder using High Level Synthesis

pp. 434-437

by Jiawei Yang, Shaohua Wang, Xiangrui Yang, Yifan Zhang, Qiang Cao, Jie Yao, Xiaodi Tan, Xiao Lin

Efficient Microprocessor Design Space Exploration via Space Partitioning

pp. 438-441

by Zijun Jiang, Yanpdi Lyu

SATL: A Spatial Architecture Rapid Prototyping Framework for Irregular Applications Acceleration

pp. 442-445

by Francesco Peverelli, Alessandro Verosimile, Davide Conficconi, Andrea Damiani, Marco D. Santambrogio

VDMig: An Adaptive Virtual Disk Migration Scheme for Cloud Block Storage System

pp. 446-453

by Guangjie Xing, Shuheng Gao, Hua Wang, Ke Zhou, Yaodong Han, Mengling Tao

Hermes: Memory-Efficient Pipeline Inference for Large Models on Edge Devices

pp. 454-461

by Xueyuan Han, Zinuo Cai, Yichu Zhang, Chongxin Fan, Junhan Liu, Ruhui Ma, Rajkumar Buyya

Opportunistic Migration for Hybrid Memories While Mitigating Aging Effects

pp. 462-469

by Aswathy N S, Hemangee K. Kapoor

HPA: A Hybrid Data Flow for PIM Architectures

pp. 470-478

by Sheng Ma, Yunping Zhao, Yuhua Tang, Yi Dai

LCKV: Learner-Cleaner Optimized Adaptive Key-Value Separated LSM-Tree Store

pp. 479-482

by Mingxuan Liu, Jianhua Gu, Tianhai Zhao

LVLDPC: Intra-Layer Variation Aware LDPC Coding for 3D TLC NAND Flash Memory

pp. 483-486

by Lanlan Cui, Meng Zhang, Fei Wu

UniCoMo: A Unified Learning-Based Cost Model for Tensorized Program Tuning

pp. 487-495

by Zihan Wang, Lei Gong, Wenqi Lou, Qianyu Cheng, Xianglan Chen, Chao Wang, Xuehai Zhou

SHEEO: Continuous Energy Efficiency Optimization in Autonomous Embedded Systems

pp. 496-503

by Xinkai Wang, Chao Li, Lingyu Sun, Qizheng Lyu, Xiaofeng Hou, Jingwen Leng, Minyi Guo

AutoSparse: A Source-to-Source Format and Schedule Auto- Tuning Framework for Sparse Tensor Program

pp. 504-512

by Xiangjun Qu, Lei Gong, Wenqi Lou, Qianyu Cheng, Xianglan Chen, Chao Wang, Xuehai Zhou

MIST: Efficient Mixed-Precision Preconditioning Through Iterative Sparse- Triangular Solver Design

pp. 513-516

by Haoyuan Zhang, Yidong Chen, Wenpeng Ma, Wu Yuan, Jian Zhang, Zhonghua Lu

Deep Recommender Models Inference: Automatic Asymmetric Data Flow Optimization

pp. 517-520

by Giuseppe Ruggeri, Renzo Andri, Daniele Jahier Pagliari, Lukas Cavigelli

MOTPE/D: Hardware and Algorithm Co-design for Reconfigurable Neuromorphic Processor

pp. 521-524

by Yuan Li, Renzhi Chen, Zhijie Yang, Xun Xiao, Jingyue Zhao, Zhenhua Zhu, Huadong Dai, Yuhua Tang, Weixia Xu, Li Luo, Lei Wang

Mera: Memory Reduction and Acceleration for Quantum Circuit Simulation via Redundancy Exploration

pp. 525-533

by Yuhong Song, Edwin Hsing-Mean Sha, Longshan Xu, Qingfeng Zhuge, Zili Shao

A Joint Optimization of Buffer and Splitter Insertion for Phase-Skipping Adiabatic Quantum - Flux - Parametron Circuits

pp. 534-541

by Robert S. Aviles, Peter A. Beerel

A Quantum Method to Match Vector Boolean Functions using Simon's Solver

pp. 542-549

by Marco Venere, Alessandro Barenghi, Gerardo Pelosi

MOSQ: Accelerating Classical Simulation of UCCSD Ansatz Circuits using Merged Operation

pp. 550-557

by Seungwoo Choi, Enhyeok Jang, Youngmin Kim, Won Woo Ro

AceMiner: Accelerating Graph Pattern Matching using PIM with Optimized Cache System

pp. 558-565

by Liang Yan, Xiaoyang Lu, Xiaoming Chen, Sheng Xu, Xingqi Zou, Yinhe Han, Xian-He Sun

Hardware Cache Locking for All Memory Updates

pp. 566-574

by Ashkan Asgharzadeh, Eduardo José Gómez-Hernández, Juan M. Cebrian, Stefanos Kaxiras, Alberto Ros

CacheTrimmer: Adaptive Cache File Trimming for Optimized Performance and Lifetime on Mobile Devices

pp. 575-582

by Yi Zhang, Yunpeng Song, Wentong Li, Yiyang Huang, Dingcui Yu, Mengyang Ma, Liang Shi

CCacheSim: A Circuit-Architecture Cross-Level Simulation Framework for SRAM-Based in-Cache Computing System Evaluation

pp. 583-590

by Baiqing Zhong, Mingyu Wang, Yicong Zhang, Xiaojie Li, Zhiyi Yu

VEGA: Implementing a Versatile and Efficient Deep Learning Processor with Graph-Based ALU

pp. 591-598

by Wenqiang Wang, Yuzhou Chen, Guanting Huo, Guanghui He, Ningyi Xu

FloatMax: An Efficient Accelerator for Transformer-Based Models Exploiting Tensor-Wise Adaptive Floating-Point Quantization

pp. 599-607

by Seoho Chung, Kwangrae Kim, Soomin Rho, Chanhoon Kim, Ki-Seok Chung

EN-T: Optimizing Tensor Computing Engines Performance via Encoder-Based Methodology

pp. 608-615

by Qizhe Wu, Yuchen Gui, Zhichen Zeng, Xiaotian Wang, Huawen Liang, Xi Jin

SLIDE-x-ML: System-Level Infrastructure for Dataset E-xtraction and Machine Learning Framework for High-Level Synthesis Estimations

pp. 616-619

by Vittoriano Muttillo, Vincenzo Stoico, Marco Santic, Giacomo Valente, Luigi Pomante, Daniele Frigioni

Early: An Importance-Aware Early Firing and Exit for SNN Acceleration

pp. 624-627

by Xuan Zhang, Zhuoran Song, Peng Zhou, Xing Li, Xueyuan Liu, Xiaolong Lin, Zhezhi He, Li Jiang, Naifeng Jing, Xiaoyao Liang

Vision Transformer Inference on a CNN Accelerator

pp. 628-636

by Changjae Yi, Hyunsu Moh, Soonhoi Ha

WOLT: Transparent Deployment of ML Workloads on Lightweight Many-Accelerator Architectures

pp. 637-644

by Kuan-Lin Chiu, Guy Eichler, Chuan-Tung Lin, Giuseppe Di Guglielmo, Luca P. Carloni

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