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2014 IEEE International Test Conference (ITC)

Oct. 20 2014 to Oct. 23 2014

Seattle, WA, USA

Table of Contents

Title pageFreely available from IEEE.pp. i-i
Copyright pageFreely available from IEEE.pp. ii-ii
Table of contentsFreely available from IEEE.pp. iii-xiv
Welcome messageFreely available from IEEE.pp. 1-2
by Michael Purtell, Subhasish Mitra
Steering committeeFreely available from IEEE.pp. 2-4
ITC 2014 Paper Awards [2 awards]Freely available from IEEE.pp. 4-5
Technical Program CommitteeFreely available from IEEE.pp. 5-7
ITC2015 call for papersFreely available from IEEE.pp. 1-1
Plenary keynote address tuesdayFreely available from IEEE.pp. 8-9
Plenary keynote panel WednssdayFreely available from IEEE.pp. 9-10
Plenary keynote address thursdayFreely available from IEEE.pp. 10-11
Process defect trends and strategic test gapsFull-text access may be available. Sign in or learn about subscription options.pp. 1-8
by Paul G Ryan, Irfan Aziz, William B Howell, Teresa K Janczak, Davia J Lu
On the testing of hazard activated open defectsFull-text access may be available. Sign in or learn about subscription options.pp. 1-6
by Chao Han, Adit D. Singh
Protecting against emerging vmin failures in advanced technology nodesFull-text access may be available. Sign in or learn about subscription options.pp. 1-7
by J. K. Jerry Lee, Amr Haggag, William Eklow
Low cost back end signal processing driven bandwidth interleaved signal acquisition using free running undersampling clocks and mixing signalsFull-text access may be available. Sign in or learn about subscription options.pp. 1-10
by Nicholas L. Tzou, Debesh Bhatta, Abhijit Chatterjee
Analog fault models: Back to the future?Full-text access may be available. Sign in or learn about subscription options.pp. 1-1
by Mani Soma
Practical random sampling of potential defects for analog fault simulationFull-text access may be available. Sign in or learn about subscription options.pp. 1-10
by Stephen Sunter, Krzysztof Jurga, Peter Dingenen, Ronny Vanhooren
Security solutions in the first-generation Zynq All-Programmable SoCFull-text access may be available. Sign in or learn about subscription options.pp. 1-1
by Steve Trimberger
Delivering security by design in the Internet of ThingsFull-text access may be available. Sign in or learn about subscription options.pp. 1-1
by Bill Curtis
Energy-secure computer architecturesFull-text access may be available. Sign in or learn about subscription options.pp. 1-1
by Pradip Bose
Dynamic microgrids - A potential solution for enhanced resiliency in distribution systemsFull-text access may be available. Sign in or learn about subscription options.pp. 1-1
by Mani Vadari
Microgrids as a resiliency resourceFull-text access may be available. Sign in or learn about subscription options.pp. 1-1
by Kevin Schneider
Recruiting distributed resources for grid resilience: The need for transparencyFull-text access may be available. Sign in or learn about subscription options.pp. 1-1
by Alexandra von Meier
Concerns over predictability of supply and qualityFull-text access may be available. Sign in or learn about subscription options.pp. 1-1
by Carl Bowen
The desire-friction ratio of Adaptive testFull-text access may be available. Sign in or learn about subscription options.pp. 1-1
by Stacy Ajouri
Collaboration and teamwork obstaclesFull-text access may be available. Sign in or learn about subscription options.pp. 1-1
by Wesley Smith
ATE and test equipment vendors; Hardware not softwareFull-text access may be available. Sign in or learn about subscription options.pp. 1-1
by Mark Roos
Efficient testing of hierarchical core-based SOCsFull-text access may be available. Sign in or learn about subscription options.pp. 1-10
by B. Keller, K. Chakravadhanula, B. Foutz, V. Chickermane, A. Garg, R. Schoonover, J. Sage, D. Pearl, T. Snethen
Isometric test compression with low toggling activityFull-text access may be available. Sign in or learn about subscription options.pp. 1-7
by A. Kumar, M. Kassab, E. Moghaddam, N. Mukherjee, J. Rajski, S.M. Reddy, J. Tyszer, C. Wang
Achieving extreme scan compression for SoC DesignsFull-text access may be available. Sign in or learn about subscription options.pp. 1-8
by Peter Wohl, John A. Waicukauski, Jonathon E. Colburn, Milind Sonawane
Mitigating voltage droop during scan with variable shift frequencyFull-text access may be available. Sign in or learn about subscription options.pp. 1-8
by John Schulze, Ryan Tally
At-speed capture power reduction using layout-aware granular clock gate enable controlsFull-text access may be available. Sign in or learn about subscription options.pp. 1-10
by R. Shaikh, P. Wilson, K. Agarwal, H. V. Sanjay, R. Tiwari, K. Lath, S. Ravi
Fast BIST of I/O Pin AC specifications and inter-chip delaysFull-text access may be available. Sign in or learn about subscription options.pp. 1-8
by Stephen Sunter, Saghir A. Shaikh, Qing Lin
Latent defect detection in microcontroller embedded flash test using device stress and wordline outlier screeningFull-text access may be available. Sign in or learn about subscription options.pp. 1-7
by Andreas Kux, Rudolf Ullmann, Thomas Kern, Roland Strunz, Hanno Melzner, Stephan Beuven, Andreas Haase
Statistical silicon results of dynamic power integrity control of ATE for eliminating overkills and underkillsFull-text access may be available. Sign in or learn about subscription options.pp. 1-10
by Masahiro Ishida, Takashi Kusaka, Toru Nakura, Satoshi Komatsu, Kunihiro Asada
Challenges of testing 100M chipsFull-text access may be available. Sign in or learn about subscription options.pp. 1-1
by Sajjad Pagarkar
Low-cost phase noise testing of complex RF ICs using standard digital ATEFull-text access may be available. Sign in or learn about subscription options.pp. 1-9
by Stephane David-Grignot, Florence Azais, Laurent Latorre, Francois Lefevre
Market opportunities and testing challenges for millimeter-wave radios and radarsFull-text access may be available. Sign in or learn about subscription options.pp. 1-1
by Brian Floyd
A novel RF self test for a combo SoC on digital ATE with multi-site applicationsFull-text access may be available. Sign in or learn about subscription options.pp. 1-8
by Chun-Hsien Peng, ChiaYu Yang, Adonis Tsu, Chung-Jin Tsai, Yosen Chen, C.-Y. Lin, Kai Hong, Kaipon Kao, Paul Liang, C.-L. Tsai, Charles Chien, H.-C. Hwang
Low-distortion signal generation for ADC testingFull-text access may be available. Sign in or learn about subscription options.pp. 1-10
by Fumitaka Abe, Yutaro Kobayashi, Kenji Sawada, Keisuke Kato, Osamu Kobayashi, Haruo Kobayashi
A built-in self-test circuit for jitter tolerance measurement in high-speed wireline receiversFull-text access may be available. Sign in or learn about subscription options.pp. 1-6
by Myeong-Jae Park, Jaeha Kim
Teaching an old dog new tricks: Views on the future of mixed-signal IC designFull-text access may be available. Sign in or learn about subscription options.pp. 1-1
by Boris Murmann
Top ten challenges in Big Data security and privacyFull-text access may be available. Sign in or learn about subscription options.pp. 1-1
by Praveen K. Murthy
Software in a hardware view: New models for HW-dependent software in SoC verification and testFull-text access may be available. Sign in or learn about subscription options.pp. 1-9
by Carlos Villarraga, Bernard Schmidt, Binghao Bao, Rakesh Raman, Christian Bartsch, Thomas Fehmel, Dominik Stoffel, Wolfgang Kunz
Compositional verification using formal analysis for a flight critical systemFull-text access may be available. Sign in or learn about subscription options.pp. 1-1
by Guillaume Brat
Design, technology and yield in the post-moore eraFull-text access may be available. Sign in or learn about subscription options.pp. 1-1
by Greg Yeric
The importance of DFX, a foundry perspectiveFull-text access may be available. Sign in or learn about subscription options.pp. 1-6
by Saman Adham, Jonathan Chang, H.J. Liao, John Hung, Ting-Hua Hsieh
Yield and performance improvement through technology-design co-optimization in advanced technology nodesFull-text access may be available. Sign in or learn about subscription options.pp. 1-1
by Yue Liang
Managing signal, power and thermal integrity for 3D integrationFull-text access may be available. Sign in or learn about subscription options.pp. 1-1
by Madhavan Swaminathan
Direct probing on large-array fine-pitch micro-bumps of a wide-I/O logic-memory interfaceFull-text access may be available. Sign in or learn about subscription options.pp. 1-10
by Erik Jan Marinissen, Bart De Wachter, Ken Smith, Jorg Kiesewetter, Mottaqiallah Taouil, Said Hamdioui
Wafer Level Chip Scale Package copper pillar probingFull-text access may be available. Sign in or learn about subscription options.pp. 1-6
by Hao Chen, Hung-Chih Lin, Ching-Nen Peng, Min-Jer Wang
A tale of two lives: Under test and in the wildFull-text access may be available. Sign in or learn about subscription options.pp. 1-1
by Bianca Schroeder
Soft error resiliency characterization and improvement on IBM BlueGene/Q processor using accelerated proton irradiationFull-text access may be available. Sign in or learn about subscription options.pp. 1-6
by Chen-Yong Cher, K. Paul Muller, Ruud A. Haring, David L. Satterfield, Thomas E. Musta, Thomas M. Gooding, Kristan D. Davis, Marc B. Dombrowa, Gerard V. Kopcsay, Robert M. Senger, Yutaka Sugawara, Krishnan Sugavanam
Efficient RAS support for die-stacked DRAMFull-text access may be available. Sign in or learn about subscription options.pp. 1-10
by Hyeran Jeon, Gabriel H. Loh, Murali Annavaram
Systematic approach for trim test time optimization: Case study on a multi-core RF SOCFull-text access may be available. Sign in or learn about subscription options.pp. 1-9
by Rajesh Mittal, Mudasir Kawoosa, Rubin A. Parekhji
Thermal-aware mobile SoC design and test in 14nm finfet technologyFull-text access may be available. Sign in or learn about subscription options.pp. 1-1
by Bong Hyun Lee
Robustness of TAP-based scan networksFull-text access may be available. Sign in or learn about subscription options.pp. 1-10
by Farrokh Ghani Zadegan, Gunnar Carlsson, Erik Larsson
Trading-off on-die observability for cache minimum supply voltage reduction in system-on-chip (SoC) processorsFull-text access may be available. Sign in or learn about subscription options.pp. 1-1
by Keith Bowman, Alex Park, Venkat Narayanan, Francois Atallah, Alain Artieri, Sei Seung Yoon, Kendrick Yuen, David Hansquine
Design, test & repair methodology for FinFET-based memoriesFull-text access may be available. Sign in or learn about subscription options.pp. 1-1
by Yervant Zorian
A Tag based solution for efficient utilization of efuse for memory repairFull-text access may be available. Sign in or learn about subscription options.pp. 1-7
by Harsharaj Ellur, Kalpesh Shah
Spatio-temporal wafer-level correlation modeling with progressive sampling: A pathway to HVM yield estimationFull-text access may be available. Sign in or learn about subscription options.pp. 1-10
by Ali Ahmadi, Ke Huang, Suriyaprakash Natarajan, John M. Carulli, Yiorgos Makris
Yield optimization using advanced statistical correlation methodsFull-text access may be available. Sign in or learn about subscription options.pp. 1-10
by Jeff Tikkanen, Sebastian Siatkowski, Nik Sumikawa, Li-C. Wang, Magdy S. Abadir
Big data and testFull-text access may be available. Sign in or learn about subscription options.pp. 1-1
by Anne Gattiker
Bayesian model fusion: Enabling test cost reduction of analog/RF circuits via wafer-level spatial variation modelingFull-text access may be available. Sign in or learn about subscription options.pp. 1-10
by Shanghang Zhang, Xin Li, R. D. Blanton, Jose Machado da Silva, John M. Carulli, Kenneth M. Butler
IC laser trimming speed-up through wafer-level spatial correlation modelingFull-text access may be available. Sign in or learn about subscription options.pp. 1-7
by Constantinos Xanthopoulos, Ke Huang, Abbas Poonawala, Amit Nahar, Bob Orr, John M. Carulli, Yiorgos Makris
Design and test of analog circuits towards sub-ppm levelFull-text access may be available. Sign in or learn about subscription options.pp. 1-2
by Georges Gielen, Wim Dobbelaere, Ronny Vanhooren, Anthony Coyette, Baris Esen
Redundancy architectures for channel-based 3D DRAM yield improvementFull-text access may be available. Sign in or learn about subscription options.pp. 1-7
by Bing-Yang Lin, Wan-Ting Chiang, Cheng-Wen Wu, Mincent Lee, Hung-Chih Lin, Ching-Nen Peng, Min-Jer Wang
Vesuvius-3D: A 3D-DfT demonstratorFull-text access may be available. Sign in or learn about subscription options.pp. 1-10
by Erik Jan Marinissen, Bart De Wachter, Stephen O'Loughlin, Sergej Deutsch, Christos Papameletis, Tobias Burgherr
A distributed, reconfigurable, and reusable bist infrastructure for 3D-stacked ICsFull-text access may be available. Sign in or learn about subscription options.pp. 1-10
by Mukesh Agrawal, Krishnendu Chakrabarty, Bill Eklow
Interposer test: Testing PCBs that have shrunk 100xFull-text access may be available. Sign in or learn about subscription options.pp. 1-1
by TM Mak
Knowledge discovery and knowledge transfer in board-level functional fault diagnosisFull-text access may be available. Sign in or learn about subscription options.pp. 1-10
by Fangming Ye, Zhaobo Zhang, Krishnendu Chakrabarty, Xinli Gu
Board manufacturing test correlation to IC manufacturing testFull-text access may be available. Sign in or learn about subscription options.pp. 1-8
by C. Glenn Shirley, W. Robert Daasch, Phil Nigh, Zoe Conroy
On-chip constrained random stimuli generation for post-silicon validation using compact masksFull-text access may be available. Sign in or learn about subscription options.pp. 1-10
by Xiaobing Shi, Nicola Nicolici
Emulation and its connection to testFull-text access may be available. Sign in or learn about subscription options.pp. 1-1
by Kenneth Larsen
Clustering-based failure triage for RTL regression debuggingFull-text access may be available. Sign in or learn about subscription options.pp. 1-10
by Zissis Poulos, Andreas Veneris
A reusable BIST with software assisted repair technology for improved memory and IO debug, validation and test timeFull-text access may be available. Sign in or learn about subscription options.pp. 1-10
by Bruce Querbach, Rahul Khanna, David Blankenbeckler, Yulan Zhang, Ronald T Anderson, David G Ellis, Zale T Schoenborn, Sabyasachi Deyati, Patrick Chiang
Analytical MRAM testFull-text access may be available. Sign in or learn about subscription options.pp. 1-10
by Raphael Robertazzi, Janusz Nowak, Jonathan Sun
Read disturb fault detection in STT-MRAMFull-text access may be available. Sign in or learn about subscription options.pp. 1-7
by Rajendra Bishnoi, Mojtaba Ebrahimi, Fabian Oboril, Mehdi B. Tahoori
Intra-die process variation aware anomaly detection in FPGAsFull-text access may be available. Sign in or learn about subscription options.pp. 1-6
by Youngok Pino, Vinayaka Jyothi, Matthew French
Feature engineering with canonical analysis for effective statistical tests screening test escapesFull-text access may be available. Sign in or learn about subscription options.pp. 1-10
by Fan Lin, Chun-Kai Hsu, Kwang-Ting Cheng
Logic characterization vehicle design for maximal information extraction for yield learningFull-text access may be available. Sign in or learn about subscription options.pp. 1-10
by R. D. Blanton, Ben Niewenhuis, Carl Taylor
The case for analyzing system level failures using structural patternsFull-text access may be available. Sign in or learn about subscription options.pp. 1-1
by Harry H. Chen
EAGLE: A regression model for fault coverage estimation using a simulation based metricFull-text access may be available. Sign in or learn about subscription options.pp. 1-10
by Shahrzad Mirkhani, Jacob A. Abraham
Comparing the effectiveness of cache-resident tests against cycleaccurate deterministic functional patternsFull-text access may be available. Sign in or learn about subscription options.pp. 1-8
by Sankar Gurumurthy, Mustansir Pratapgarhwala, Curtis Gilgan, Jeff Rearick
Fault sharing in a copy-on-write based ATPG systemFull-text access may be available. Sign in or learn about subscription options.pp. 1-8
by X. Cai, P. Wohl, D. Martin
Test pattern generation in presence of unknown values based on restricted symbolic logicFull-text access may be available. Sign in or learn about subscription options.pp. 1-10
by Dominik Erb, Karsten Scheibler, Michael A. Kochte, Matthias Sauer, Hans-Joachim Wunderlich, Bernd Becker
Efficient SAT-based ATPG techniques for all multiple stuck-at faultsFull-text access may be available. Sign in or learn about subscription options.pp. 1-10
by Masahiro Fujita, Alan Mishchenko
Testing silicon TV tuners on ATE without TV signal generatorFull-text access may be available. Sign in or learn about subscription options.pp. 1-9
by Y. Fan, A. Verma, J. Janney, S. Kumar
A self-tuning architecture for buck converters based on alternative testFull-text access may be available. Sign in or learn about subscription options.pp. 1-10
by X. Wang, K. Blanchard, S. Estella, A. Chatterjee
Fast co-test of linearity and spectral performance with non-coherent sampled and amplitude clipped dataFull-text access may be available. Sign in or learn about subscription options.pp. 1-8
by Li Xu, Degang Chen
Board security enhancement using new locking SIB-based architecturesFull-text access may be available. Sign in or learn about subscription options.pp. 1-10
by Jennifer Dworak, Zoe Conroy, Al Crouch, John Potter
Counterfeit IC detection using light emissionFull-text access may be available. Sign in or learn about subscription options.pp. 1-8
by Peilin Song, Franco Stellari, Alan Weger
Test-mode-only scan attack and countermeasure for contemporary scan architecturesFull-text access may be available. Sign in or learn about subscription options.pp. 1-8
by Samah Mohamed Saeed, Sk Subidh Ali, Ozgur Sinanoglu, Ramesh Karri
Improving test compression with scan feedforward techniquesFull-text access may be available. Sign in or learn about subscription options.pp. 1-10
by Sreenivaas S. Muthyala, Nur A. Touba
A diagnosis-friendly LBIST architecture with property checkingFull-text access may be available. Sign in or learn about subscription options.pp. 1-9
by Sarvesh Prabhu, Vineeth V. Acharya, Sharad Bagri, Michael S. Hsiao
FAST-BIST: Faster-than-at-Speed BIST targeting hidden delay defectsFull-text access may be available. Sign in or learn about subscription options.pp. 1-8
by Sybille Hellebrand, Thomas Indlekofer, Matthias Kampmann, Michael A. Kochte, Chang Liu, Hans-Joachim Wunderlich
An efficient diagnosis-aware pattern generation procedure for transition faultsFull-text access may be available. Sign in or learn about subscription options.pp. 1-10
by Kuen-Jong Lee, Cheng-Hung Wu
Divide and conquer diagnosis for multiple defectsFull-text access may be available. Sign in or learn about subscription options.pp. 1-8
by Shih-Min Chao, Po-Juei Chen, Jing-Yu Chen, Po-Hao Chen, Ang-Feng Lin, James C.-M. Li, Pei-Ying Hsueh, Chun-Yi Kuo, Ying-Yen Chen, Jih-Nung Li
Massive signal tracing using on-chip DRAM for in-system silicon debugFull-text access may be available. Sign in or learn about subscription options.pp. 1-10
by Sergej Deutsch, Krishnendu Chakrabarty
Error prediction and detection methodologies for reliable circuit operation under NBTIFull-text access may be available. Sign in or learn about subscription options.pp. 1-10
by Julio Vazquez-Hernandez
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