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Proceedings International Test Conference 2001 (Cat. No.01CH37260)

Oct. 30 2001 to Nov. 1 2001

Baltimore, Maryland

ISBN: 0-7803-7171-2

Table of Contents

Proceedings International Test Conference 2001 [front matter]Freely available from IEEE.pp. i,ii,iii,iv,v,vi,vii,viii,ix,x,xi,xii,xiii,xiv
INTRODUCTORY SECTION
Welcoming MessageFreely available from IEEE.pp. 1
INTRODUCTORY SECTION
Steering Committee and SubcommitteesFreely available from IEEE.pp. 2
INTRODUCTORY SECTION
Technical Program CommitteeFreely available from IEEE.pp. 4
INTRODUCTORY SECTION
ITC Technical Paper Evaluation and Selection ProcessFreely available from IEEE.pp. 8
INTRODUCTORY SECTION
2000 Paper AwardsFreely available from IEEE.pp. 9
INTRODUCTORY SECTION
TTTC: Test Technology Technical CouncilFreely available from IEEE.pp. 14
INTRODUCTORY SECTION
Technical Paper ReviewersFreely available from IEEE.pp. 17
INTRODUCTORY SECTION
Author IndexFreely available from IEEE.pp. 1200
SPECIAL PANEL: CHANGING ECONOMICS OF SOC TESTING: WHO OWNS THE MARKET?
CHANGING ECONOMICS OF SOC TESTING: WHO OWNS THE MARKET?Full-text access may be available. Sign in or learn about subscription options.pp. 23
SPECIAL PANEL: CHANGING ECONOMICS OF SOC TESTING: WHO OWNS THE MARKET?
Adding Value to SOC Testing While Lowering CostsFull-text access may be available. Sign in or learn about subscription options.pp. 24
SPECIAL PANEL: CHANGING ECONOMICS OF SOC TESTING: WHO OWNS THE MARKET?
Changing Economics of SOC Testing: Who Owns the Market?Full-text access may be available. Sign in or learn about subscription options.pp. 25
SPECIAL PANEL: CHANGING ECONOMICS OF SOC TESTING: WHO OWNS THE MARKET?
SOC Test Challenges for the New MillenniumFull-text access may be available. Sign in or learn about subscription options.pp. 26
SPECIAL PANEL: CHANGING ECONOMICS OF SOC TESTING: WHO OWNS THE MARKET?
Bridging the GapFull-text access may be available. Sign in or learn about subscription options.pp. 27
SPECIAL PANEL: STRUCTURED TEST: THEN AND NOW
STRUCTURED TEST: THEN AND NOWFull-text access may be available. Sign in or learn about subscription options.pp. 28
SPECIAL PANEL: STRUCTURED TEST: THEN AND NOW
Structured Test, Then and NowFull-text access may be available. Sign in or learn about subscription options.pp. 29
SESSION 1: PLENARY
Keynote Address: Test Trade-offs: The View from Wall StreetFreely available from IEEE.pp. 12
SESSION 1: PLENARY
Invited Address: Today's Test Choices: Anticipate, Adapt, Partner or PerishFreely available from IEEE.pp. 13
SESSION 2: IEEE 1149 — BEYOND DC TESTING AT BOARD TEST
AC-JTAG: Empowering JTAG beyond Testing DC NetsFull-text access may be available. Sign in or learn about subscription options.pp. 30
SESSION 2: IEEE 1149 — BEYOND DC TESTING AT BOARD TEST
A General Purpose 1149.4 IC with HF Analog Test CapabilitiesFull-text access may be available. Sign in or learn about subscription options.pp. 38
SESSION 2: IEEE 1149 — BEYOND DC TESTING AT BOARD TEST
Frequency Detection-Based Boundary-Scan Testing of AC Coupled NetsFull-text access may be available. Sign in or learn about subscription options.pp. 46
SESSION 3: BIST MEDLEY
DESIGN OF COMPACTORS FOR SIGNATURE-ANALYZERS IN BUILT-IN SELF-TESTFull-text access may be available. Sign in or learn about subscription options.pp. 54
SESSION 3: BIST MEDLEY
At-Speed Logic BIST Using a Frozen Clock Testing StrategyFull-text access may be available. Sign in or learn about subscription options.pp. 64
SESSION 3: BIST MEDLEY
TACKLING TEST TRADE-OFFS FOR BIST RTL DATA PATHS: BIST AREA OVERHEAD, TEST APPLICATION TIME AND POWER DISSIPATIONFull-text access may be available. Sign in or learn about subscription options.pp. 72
SESSION 4: HOW CAN WE INPROVE IDDQ TESTING FOR DSM/VDSM?
Improved Wafer-level Spatial Analysis for IDDQ Limit SettingFull-text access may be available. Sign in or learn about subscription options.pp. 82
SESSION 4: HOW CAN WE INPROVE IDDQ TESTING FOR DSM/VDSM?
NEIGHBOR SELECTION FOR VARIANCE REDUCTION IN IDDQ and OTHER PARAMETRIC DATAFull-text access may be available. Sign in or learn about subscription options.pp. 92
SESSION 4: HOW CAN WE INPROVE IDDQ TESTING FOR DSM/VDSM?
The Future of Delta IDDQ TestingFull-text access may be available. Sign in or learn about subscription options.pp. 101
SESSION 5: PRACTICAL EXPERIENCE WITH SOC TESTING
A Building Block BIST Methodology for SOC Designs: A Case StudyFull-text access may be available. Sign in or learn about subscription options.pp. 111
SESSION 5: PRACTICAL EXPERIENCE WITH SOC TESTING
Test and Debug Strategy of the PNX8525 Nexperia™ Digital Video Platform System ChipFull-text access may be available. Sign in or learn about subscription options.pp. 121
SESSION 5: PRACTICAL EXPERIENCE WITH SOC TESTING
CTL the Language for Describing Core-Based TestFull-text access may be available. Sign in or learn about subscription options.pp. 131
SESSION 6: SOME THORNY PROBLEMS FOR ATE SOFTWARE
Split Timing Mode (STM) - Answer To Dual Frequency Domain TestingFull-text access may be available. Sign in or learn about subscription options.pp. 140
SESSION 6: SOME THORNY PROBLEMS FOR ATE SOFTWARE
Automated Translation of Legacy Code for ATEFull-text access may be available. Sign in or learn about subscription options.pp. 148
SESSION 6: SOME THORNY PROBLEMS FOR ATE SOFTWARE
REMOTE ACCESS TO ENGINEERING TEST — A CASE STUDY IN PROVIDING ENGINEERING/DIAGNOSTIC IC TEST SERVICES TO CANADIAN UNIVERSITIESFull-text access may be available. Sign in or learn about subscription options.pp. 157
SESSION 7: LECTURE SERIES — TEST AND REPAIR OF LARGE EMBEDDED DRAMS
Test and Repair of Large Embedded DRAMs: Part 1Full-text access may be available. Sign in or learn about subscription options.pp. 163
SESSION 7: LECTURE SERIES — TEST AND REPAIR OF LARGE EMBEDDED DRAMS
Test and Repair of Large Embedded DRAMs: part 2Full-text access may be available. Sign in or learn about subscription options.pp. 173
SESSION 7: LECTURE SERIES — TEST AND REPAIR OF LARGE EMBEDDED DRAMS
Test cost reduction by at-speed BISR for embedded DRAMsFull-text access may be available. Sign in or learn about subscription options.pp. 182
SESSION 8: DFT INNOVATIONS
DPDAT: DATA PATH DIRECT ACCESS TESTINGFull-text access may be available. Sign in or learn about subscription options.pp. 188
SESSION 8: DFT INNOVATIONS
A Method to Enhance the Fault Coverage Obtained by Output Response Comparison of Identical CircuitsFull-text access may be available. Sign in or learn about subscription options.pp. 196
SESSION 8: DFT INNOVATIONS
Contactless Digital Testing of IC Pin Leakage CurrentsFull-text access may be available. Sign in or learn about subscription options.pp. 204
SESSION 8: DFT INNOVATIONS
On Improving the Stuck-at Fault Coverage of Functional Test Sequences by Using Limited-Scan OperationsFull-text access may be available. Sign in or learn about subscription options.pp. 211
SESSION 9: ON-LINE TEST
Algorithm Level Re-Computing with Allocation Diversity: A Register Transfer Level Time Redundancy Based Concurrent Error Detection TechniqueFull-text access may be available. Sign in or learn about subscription options.pp. 221
SESSION 9: ON-LINE TEST
A Highly-Efficient Transparent Online Memory TestFull-text access may be available. Sign in or learn about subscription options.pp. 230
SESSION 9: ON-LINE TEST
On-line Testing and Recovery in TMR Systems for Real-Time ApplicationsFull-text access may be available. Sign in or learn about subscription options.pp. 240
SESSION 9: ON-LINE TEST
GRAAL: a Tool for Highly Dependable SRAMs GenerationFull-text access may be available. Sign in or learn about subscription options.pp. 250
SESSION 10: NOVEL TECHNIQUES FOR FAULT DIAGNOSIS
Test Response Compression and Bitmap Encoding for Embedded Memories in Manufacturing Process MonitoringFull-text access may be available. Sign in or learn about subscription options.pp. 258
SESSION 10: NOVEL TECHNIQUES FOR FAULT DIAGNOSIS
A Technique for Fault Diagnosis of Defects in Scan ChainsFull-text access may be available. Sign in or learn about subscription options.pp. 268
SESSION 10: NOVEL TECHNIQUES FOR FAULT DIAGNOSIS
Making Cause-Effect Cost Effective: Low-Resolution Fault DictionariesFull-text access may be available. Sign in or learn about subscription options.pp. 278
SESSION 10: NOVEL TECHNIQUES FOR FAULT DIAGNOSIS
Diagnosing Combinational Logic Designs Using the Single Location At-a-Time (SLAT) ParadigmFull-text access may be available. Sign in or learn about subscription options.pp. 287
SESSION 11: TESTING ABOVE A GIGAHERTZ
Testing Gigabit Multilane SerDes Interfaces with Passive Jitter Injection FiltersFull-text access may be available. Sign in or learn about subscription options.pp. 297
SESSION 11: TESTING ABOVE A GIGAHERTZ
Testing Interconnects for Noise and Skew in Gigahertz SoCsFull-text access may be available. Sign in or learn about subscription options.pp. 305
SESSION 11: TESTING ABOVE A GIGAHERTZ
A BUILT-IN TIMING PARAMETRIC MEASUREMENT UNITFull-text access may be available. Sign in or learn about subscription options.pp. 315
SESSION 11: TESTING ABOVE A GIGAHERTZ
Testing Clock Distribution Circuits Using an Analytic Signal MethodFull-text access may be available. Sign in or learn about subscription options.pp. 323
SESSION 12: TEST METHODS FOR HIGH-DENSITY MODULES
Rapid Prototyping of Time-based PDIT for Substrate NetworksFull-text access may be available. Sign in or learn about subscription options.pp. 332
SESSION 12: TEST METHODS FOR HIGH-DENSITY MODULES
Estimating Burn-In Fall-Out for Redundant MemoryFull-text access may be available. Sign in or learn about subscription options.pp. 340
SESSION 12: TEST METHODS FOR HIGH-DENSITY MODULES
Extreme-Voltage Stress Vector Generation of Analog CMOS ICs for Gate-Oxide Reliability EnhancementFull-text access may be available. Sign in or learn about subscription options.pp. 348
SESSION 13: HIGH-QUALITY TEST
Multiple-Output Propagation Transition Fault TestFull-text access may be available. Sign in or learn about subscription options.pp. 358
SESSION 13: HIGH-QUALITY TEST
Switch-level Delay Test of Domino Logic CircuitsFull-text access may be available. Sign in or learn about subscription options.pp. 367
SESSION 13: HIGH-QUALITY TEST
Implicit Functionality and Multiple Branch Coverage (IFMB): a Testability Metric for RT-LevelFull-text access may be available. Sign in or learn about subscription options.pp. 377
SESSION 14: NEW IDDX AND ENERGY TEST TECHNIQUES
Practical Application of Energy Consumption Ratio TestFull-text access may be available. Sign in or learn about subscription options.pp. 386
SESSION 14: NEW IDDX AND ENERGY TEST TECHNIQUES
Detecting Delay Faults using Power Supply Transient Signal AnalysisFull-text access may be available. Sign in or learn about subscription options.pp. 395
SESSION 14: NEW IDDX AND ENERGY TEST TECHNIQUES
A Practical Built-In Current Sensor for IDDQ TestingFull-text access may be available. Sign in or learn about subscription options.pp. 405
SESSION 15: ATE HARDWARE: IMPROVING YOUR TEST RESULTS
TEST PATH SIMULATION AND CHARACTERISATIONFull-text access may be available. Sign in or learn about subscription options.pp. 415
SESSION 15: ATE HARDWARE: IMPROVING YOUR TEST RESULTS
Testing beyond EPA: TDF Methodology Solutions MatrixFull-text access may be available. Sign in or learn about subscription options.pp. 424
SESSION 15: ATE HARDWARE: IMPROVING YOUR TEST RESULTS
Practical,Non-invasive Optical Probing for Flip-Chip DevicesFull-text access may be available. Sign in or learn about subscription options.pp. 433
SESSION 16: ADVANCED MICROPROCESSOR TEST METHODOLOGIES
Scan vs. Functional Testing - A Comparative Effectiveness Study on Motorola?s MMC2107TMFull-text access may be available. Sign in or learn about subscription options.pp. 443
SESSION 16: ADVANCED MICROPROCESSOR TEST METHODOLOGIES
Debug Methodology for the McKinley ProcessorFull-text access may be available. Sign in or learn about subscription options.pp. 451
SESSION 16: ADVANCED MICROPROCESSOR TEST METHODOLOGIES
Using a Hierarchical DfT Methodology in High Frequency Processor Designs for Improved Delay Fault TestabilityFull-text access may be available. Sign in or learn about subscription options.pp. 461
SESSION 17: LECTURE SERIES — SOLVING BOARD TEST AND IN-SYSTEM PROBLEMS
TESTING AND PROGRAMMING FLASH MEMORIES ON ASSEMBLIES DURING HIGH VOLUME PRODUCTIONFull-text access may be available. Sign in or learn about subscription options.pp. 470
SESSION 17: LECTURE SERIES — SOLVING BOARD TEST AND IN-SYSTEM PROBLEMS
Hierarchical Boundary-Scan A Scan Chip-Set SolutionFull-text access may be available. Sign in or learn about subscription options.pp. 480
SESSION 17: LECTURE SERIES — SOLVING BOARD TEST AND IN-SYSTEM PROBLEMS
A PRACTICAL GUIDE TO COMBING ICT & BOUNDARY SCAN TESTINGFull-text access may be available. Sign in or learn about subscription options.pp. 487
SESSION 18: MIXED-SIGNAL TESTING TECHNIQUES
RAMP TESTING OF ADC TRANSITION LEVELS USING FINITE RESOLUTION RAMPSFull-text access may be available. Sign in or learn about subscription options.pp. 495
SESSION 18: MIXED-SIGNAL TESTING TECHNIQUES
TEST CHALLENGES FOR SONET/SDH PHYSICAL LAYER OC3 DEVICES AND BEYONDFull-text access may be available. Sign in or learn about subscription options.pp. 502
SESSION 18: MIXED-SIGNAL TESTING TECHNIQUES
A Method to Improve SFDR with Random Interleaved Sampling MethodFull-text access may be available. Sign in or learn about subscription options.pp. 512
SESSION 19: ADVANCED TECHNIQUES FOR EMBEDDED CORE TESTING
Space and Time Compaction Schemes for Embedded CoresFull-text access may be available. Sign in or learn about subscription options.pp. 521
SESSION 19: ADVANCED TECHNIQUES FOR EMBEDDED CORE TESTING
Tailoring ATPG for Embedded TestingFull-text access may be available. Sign in or learn about subscription options.pp. 530
SESSION 19: ADVANCED TECHNIQUES FOR EMBEDDED CORE TESTING
A Case Study on t e Implementation of t e Illinois Scan ArchitectureFull-text access may be available. Sign in or learn about subscription options.pp. 538
SESSION 20: TEST GENERATION FOR CROSSTALK FAULTS
Crosstalk Test Generation on Pseudo industrial Circuits: A Case StudyFull-text access may be available. Sign in or learn about subscription options.pp. 548
SESSION 20: TEST GENERATION FOR CROSSTALK FAULTS
Delay Testing Considering Crosstalk-Induced EffectsFull-text access may be available. Sign in or learn about subscription options.pp. 558
SESSION 20: TEST GENERATION FOR CROSSTALK FAULTS
On Reducing the Target Fault List of Crosstalk-Induced Delay Faults in Synchronous Sequential CircuitsFull-text access may be available. Sign in or learn about subscription options.pp. 568
SESSION 21: MICROPROCESSOR TESTING
Test Methodology for the McKinley ProcessorFull-text access may be available. Sign in or learn about subscription options.pp. 578
SESSION 21: MICROPROCESSOR TESTING
99 % AC test coverage using only LBIST on the 1 GHz IBM S/390 zSeries 900 MicroprocessorFull-text access may be available. Sign in or learn about subscription options.pp. 586
SESSION 21: MICROPROCESSOR TESTING
MODELING AND TESTING THE GEKKO MICROPROCESSOR, AN IBM POWERPC DERIVATIVE FOR NINTENDOFull-text access may be available. Sign in or learn about subscription options.pp. 593
SESSION 22: STANDARDS AND TECHNIQUES — BOARD TEST DEVELOPMENT
TOWARDS A UNIFIED TEST PROCESS: FROM UML TO END-OF-LINE FUNCTIONAL TESTFull-text access may be available. Sign in or learn about subscription options.pp. 600
SESSION 22: STANDARDS AND TECHNIQUES — BOARD TEST DEVELOPMENT
DYNAMIC TESTS IN COMPLEX SYSTEMSFull-text access may be available. Sign in or learn about subscription options.pp. 609
SESSION 22: STANDARDS AND TECHNIQUES — BOARD TEST DEVELOPMENT
Unsafe Board States During PC-Based Boundary-Scan TestingFull-text access may be available. Sign in or learn about subscription options.pp. 615
SESSION 23: DELAY TEST
Too Much Delay Fault Coverage Is a Bad ThingFull-text access may be available. Sign in or learn about subscription options.pp. 624
SESSION 23: DELAY TEST
TESTING OF CRITICAL PATHS FOR DELAY FAULTSFull-text access may be available. Sign in or learn about subscription options.pp. 634
SESSION 23: DELAY TEST
Exact Path Delay Grading with Fundamental BDD OperationsFull-text access may be available. Sign in or learn about subscription options.pp. 642
SESSION 24: IDEAS FOR LOW-POWER SCAN OPERATION
Scan Array Solution for Testing Power and Testing TimeFull-text access may be available. Sign in or learn about subscription options.pp. 652
SESSION 24: IDEAS FOR LOW-POWER SCAN OPERATION
A Token Scan Architecture for Low Power TestingFull-text access may be available. Sign in or learn about subscription options.pp. 660
SESSION 24: IDEAS FOR LOW-POWER SCAN OPERATION
An Analysis of Powe Reduction Techniques in Scan TestingFull-text access may be available. Sign in or learn about subscription options.pp. 670
SESSION 25: UNCOVERING AND UNDERSTANDING WHY CIRCUITS FAIL
On Efficient Error Diagnosis of Digital CircuitsFull-text access may be available. Sign in or learn about subscription options.pp. 678
SESSION 25: UNCOVERING AND UNDERSTANDING WHY CIRCUITS FAIL
A Study of Bridging Defect Probabilities on a Pentium (tm) 4 CPUFull-text access may be available. Sign in or learn about subscription options.pp. 688
SESSION 25: UNCOVERING AND UNDERSTANDING WHY CIRCUITS FAIL
FedEx - A Fast Bridging Fault ExtractorFull-text access may be available. Sign in or learn about subscription options.pp. 696
SESSION 26: ATE HW: CONQUERING THOSE STUBBORN TEST PROBLEMS
Power Supply Transient Signal Integration CircuitFull-text access may be available. Sign in or learn about subscription options.pp. 704
SESSION 26: ATE HW: CONQUERING THOSE STUBBORN TEST PROBLEMS
Scan Test Sequencing Hardware for Structural TestFull-text access may be available. Sign in or learn about subscription options.pp. 713
SESSION 27: ADVANCES IN SCAN TESTING
Tester Retargetable PatternsFull-text access may be available. Sign in or learn about subscription options.pp. 721
SESSION 27: ADVANCES IN SCAN TESTING
On RTL Scan DesignFull-text access may be available. Sign in or learn about subscription options.pp. 728
SESSION 27: ADVANCES IN SCAN TESTING
Enhanced Reduced Pin-Count Test for Full-Scan DesignFull-text access may be available. Sign in or learn about subscription options.pp. 738
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