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Proceedings of 7th International Conference on VLSI Design

Jan. 5 1994 to Jan. 8 1994

Calcutta, India

Table of Contents

SEMU: a parallel processing system for timing simulation of digital CMOS VLSI circuitsFull-text access may be available. Sign in or learn about subscription options.pp. 33,34,35,36,37,38
by A. Asthana, M. Laznovsky, B. Mathews
Logic simulation using an asynchronous parallel discrete-event simulation model on a SIMD machineFull-text access may be available. Sign in or learn about subscription options.pp. 29,30,31,32
by S. Seth, L. Gowen, M. Payne, D. Sylwester
FAST: FPGA targeted RTL structure synthesis techniqueFull-text access may be available. Sign in or learn about subscription options.pp. 21,22,23,24
by A.R. Naseer, M. Balakrishnan, A. Kumar
ILP-based scheduling with time and resource constraints in high level synthesisFull-text access may be available. Sign in or learn about subscription options.pp. 17,18,19,20
by S. Chaudhuri, R.A. Walker
An empirical study on the effects of physical design in high-level synthesisFull-text access may be available. Sign in or learn about subscription options.pp. 11,12,13,14,15,16
by P.K. Jha, C. Ramachandran, N.D. Dutt, F.J. Kurdahi
Application of high-level synthesis in an industrial projectFull-text access may be available. Sign in or learn about subscription options.pp. 5,6,7,8,9,10
by A. Hemani, B. Karlsson, M. Fredriksson, K. Nordqvist, B. Fjellborg
Proceedings of 7th International Conference on VLSI DesignFreely available from IEEE.pp. 0_1-0_1
Ultra fine-grain template-driven synthesisFull-text access may be available. Sign in or learn about subscription options.pp. 25,26,27,28
by D.J. Kolson, N. Dutt, A. Nicolau
CM-SIM: a parallel circuit simulator on a distributed memory multiprocessorFull-text access may be available. Sign in or learn about subscription options.pp. 39,40,41,42,43,44
by C.V. Ramamoorthy, V. Vij
Parallel model evaluation for circuit simulation on the PACE multiprocessorFull-text access may be available. Sign in or learn about subscription options.pp. 45,46,47,48
by P. Agrawal, S. Goil, S. Liu, J.A. Trotter
Time- and cost-optimal parallel algorithms for the dominance and visibility graphs /spl lsqb/IC design/spl rsqb/Full-text access may be available. Sign in or learn about subscription options.pp. 49,50,51,52
by D. Bhagavathi, S. Olariu, J.L. Schwing, J. Zhang
Analog modeling using event-driven HDL'sFull-text access may be available. Sign in or learn about subscription options.pp. 53,54,55,56
by D. Dumlugol, D. Webber
A SPICE model of RLGC transmission line with error controlFull-text access may be available. Sign in or learn about subscription options.pp. 57,58,59,60
by Qingjian Yu
Multiple fault testing in analog circuitsFull-text access may be available. Sign in or learn about subscription options.pp. 61,62,63,64,65,66
by N. Ben Hamida, B. Kaminska
The design of analog self-checking circuitsFull-text access may be available. Sign in or learn about subscription options.pp. 67,68,69,70
by B. Vinnakota, R. Harjani
OTA based neural network architectures with on-chip tuning of synapsesFull-text access may be available. Sign in or learn about subscription options.pp. 71,72,73,74,75,76
by J. Ghosh, P. LaCour, S. Jackson
TWTXBB: a low latency, high throughput multiplier architecture using a new 4/spl rarr/2 compressorFull-text access may be available. Sign in or learn about subscription options.pp. 77,78,79,80,81,82
by D. Ghosh, S.K. Nandy, K. Parthasarathy
Calculation of minimum number of registers in arbitrary life time chartFull-text access may be available. Sign in or learn about subscription options.pp. 83,84,85,86
by K.K. Parhi
A VLSI architecture of an inverse discrete cosine transformFull-text access may be available. Sign in or learn about subscription options.pp. 87,88,89,90
by A.K. Bhattacharya, S.S. Haider
A fast algorithm for performing vector quantization and its VLSI implementationFull-text access may be available. Sign in or learn about subscription options.pp. 91,92,93,94
by Heonchul Park, V.K. Prasanna
A 600 MHz half-bit level pipelined multiplier macrocellFull-text access may be available. Sign in or learn about subscription options.pp. 95,96,97,98,99,100
by D. Ghosh, S. Sural, S.K. Nandy
A three-stage partial scan design method using the sequential circuit flow graphFull-text access may be available. Sign in or learn about subscription options.pp. 101,102,103,104,105,106
by Shang-E Tai, D. Bhattacharya
Simulated annealing for target-oriented partial scanFull-text access may be available. Sign in or learn about subscription options.pp. 107,108,109,110,111,112
by C.P. Ravikumar, H. Rasheed
A test function architecture for interconnected finite state machinesFull-text access may be available. Sign in or learn about subscription options.pp. 113,114,115,116
by S. Kanjilal, S.T. Chakradhar, V.D. Agrawal
A BIST PLA design for high fault coverage and testing by an interleavingly crosspoint countingFull-text access may be available. Sign in or learn about subscription options.pp. 117,118,119,120,121,122
by M.A. Mottalib, P. Dasgupta
Testability properties of local circuit transformations with respect to the robust path-delay-fault modelFull-text access may be available. Sign in or learn about subscription options.pp. 123,124,125,126
by H. Hengster, R. Drechsler, B. Becker
Flipping modules to improve circuit performance and routabilityFull-text access may be available. Sign in or learn about subscription options.pp. 127,128,129,130,131,132
by K. Ahn, S. Sahni
A new genetic algorithm for the channel routing problemFull-text access may be available. Sign in or learn about subscription options.pp. 133,134,135,136
by J. Lienig, K. Thulasiraman
High performance over-the-cell routingFull-text access may be available. Sign in or learn about subscription options.pp. 137,138,139,140,141,142
by J.E. Crenshaw, S. Tragoudas, N.A. Sherwani
Over-the-cell routing algorithms for industrial cell modelsFull-text access may be available. Sign in or learn about subscription options.pp. 143,144,145,146,147,148
by S. Bhingarde, R. Khawaja, A. Panyam, N.A. Sherwani
Two-layer wiring with pin preassignments is easier if the power supply nets are already generatedFull-text access may be available. Sign in or learn about subscription options.pp. 149,150,151,152,153,154
by P. Molitor, U. Sparmann, D. Wagner
Rapid technology projection for high-level synthesisFull-text access may be available. Sign in or learn about subscription options.pp. 155,156,157,158
by P.K. Jha, N.D. Dutt
Behavioral design and prototyping of a fail-safe systemFull-text access may be available. Sign in or learn about subscription options.pp. 159,160,161,162
by Yinghua Min, Yutang Zhou, Zhongcheng Li, Cheng Ye, Yuqi Pan
BINET: an algorithm for solving the binding problemFull-text access may be available. Sign in or learn about subscription options.pp. 163,164,165,166,167,168
by A. Mujumdar, M. Rim, R. Jain, R. De Leone
A CAD tool for design of on-chip store and generate schemeFull-text access may be available. Sign in or learn about subscription options.pp. 169,170,171,172,173,174
by S. Nandi, B. Vamsi, P. Pal Chaudhuri
HSIM1 and HSIM2: object oriented algorithms for VHDL simulationFull-text access may be available. Sign in or learn about subscription options.pp. 175,176,177,178
by N. Ganguly, V. Pitchumani
I/sub DDQ/ measurement based diagnosis of bridging faults in full scan circuitsFull-text access may be available. Sign in or learn about subscription options.pp. 179,180,181,182
by S. Chakravarty, S. Suresh
I/sub DDQ/ detection of CMOS bridging faults by stuck-at fault testsFull-text access may be available. Sign in or learn about subscription options.pp. 183,184,185,186
by S. Hwang, R. Rajsuman, S. Davidson
The effect of built-in current sensors (BICS) on operational and test performance /spl lsqb/CMOS ICs/spl rsqb/Full-text access may be available. Sign in or learn about subscription options.pp. 187,188,189,190
by S.M. Menon, Y.K. Malaiya, A.P. Jayasumana, C.Q. Tong
On testability of differential split-level CMOS circuitsFull-text access may be available. Sign in or learn about subscription options.pp. 191,192,193,194,195,196
by S.M. Aziz, W.A.J. Waller
Testable realizations of CMOS combinational circuits for voltage and current testingFull-text access may be available. Sign in or learn about subscription options.pp. 197,198,199,200,201,202
by K. Biswas, S. Rai
On the synthesis of gate matrix layoutFull-text access may be available. Sign in or learn about subscription options.pp. 203,204,205,206
by R. Agarwal, I. Sen Gupta
An efficient hybrid heuristic for the gate matrix layout problem in VLSI designFull-text access may be available. Sign in or learn about subscription options.pp. 207,208,209,210
by T. Bagchi, S.K. Das
SAGA : a unification of the genetic algorithm with simulated annealing and its application to macro-cell placementFull-text access may be available. Sign in or learn about subscription options.pp. 211,212,213,214
by H. Esbensen, P. Mazumder
GLOVE: a graph-based layout verifierFull-text access may be available. Sign in or learn about subscription options.pp. 215,216,217,218,219,220
by C.S. Bamji, J. Allen
A sea-of-gates style FPGA placement algorithmFull-text access may be available. Sign in or learn about subscription options.pp. 221,222,223,224
by K. Roy, Bingzhong Guan, C. Sechen
A methodology for architecture synthesis of cascaded IIR filters on TLU FPGAsFull-text access may be available. Sign in or learn about subscription options.pp. 225,226,227,228
by G.N. Rathna, S.K. Nandy, K. Parthasarathy
High speed digital filtering on SRAM-based FPGAsFull-text access may be available. Sign in or learn about subscription options.pp. 229,230,231,232
by A. Giri, V. Visvanathan, S.K. Nandy, S.K. Ghoshal
Impact of logic module routing flexibility on the routability of antifuse-based channelled FPGA architecturesFull-text access may be available. Sign in or learn about subscription options.pp. 233,234,235,236
by M. Mehendale
Detailed routing of multi-terminal nets in FPGAsFull-text access may be available. Sign in or learn about subscription options.pp. 237,238,239,240,241,242
by A. Chowdhary, D. Bhatia
A switch-memory chip for packet switching at gigabits per secondFull-text access may be available. Sign in or learn about subscription options.pp. 243,244,245,246
by H. Kanakia
A 2K/spl times/1K space switch ASIC for use in digital exchangesFull-text access may be available. Sign in or learn about subscription options.pp. 247,248,249,250
by V. Keshava Murthy, K. Madhu Kumar, M.B. Vani, D. Jagadish Kumar, C.S. Mohan, B.S. Prasanna
Layout influenced factorization of Boolean functionsFull-text access may be available. Sign in or learn about subscription options.pp. 251,252,253,254
by A. Jaekel, S. Bandyopadhyay, A. Sengupta
On determining symmetries in inputs of logic circuitsFull-text access may be available. Sign in or learn about subscription options.pp. 255,256,257,258,259,260
by I. Pomeranz, S.M. Reddy
Energy efficient programmable computationFull-text access may be available. Sign in or learn about subscription options.pp. 261,262,263,264
by A.P. Chandrakasan, M.B. Srivastava, R.W. Brodersen
Synthesis of low power linear DSP circuits using activity metricsFull-text access may be available. Sign in or learn about subscription options.pp. 265,266,267,268,269,270
by A. Chatterjee, R.K. Roy
Power constraint scheduling of testsFull-text access may be available. Sign in or learn about subscription options.pp. 271,272,273,274
by R.M. Chou, K.K. Saluja, V.D. Agrawal
Design of an application specific VLSI chip for image rotationFull-text access may be available. Sign in or learn about subscription options.pp. 275,276,277,278
by I. Ghosh, B. Majumdar
Cellular automata based VLSI architecture for computing multiplication and inverses in GF(2/sup m/)Full-text access may be available. Sign in or learn about subscription options.pp. 279,280,281,282
by P. Pal Choudhury, R. Barua
Architecture for VLSI design of CA based byte error correcting code decodersFull-text access may be available. Sign in or learn about subscription options.pp. 283,284,285,286
by D.R. Chowdhury, P.P. Chaudhuri
VLSI architecture for HDTV motion estimation based on block-matching algorithmFull-text access may be available. Sign in or learn about subscription options.pp. 287,288,289,290
by Feng-Ming Yang, S. Wolter, R. Laur
ACE: a VLSI chip for Galois field GF(2/sup m/) based exponentiationFull-text access may be available. Sign in or learn about subscription options.pp. 291,292,293,294,295,296
by M. Kovac, N. Ranganathan
An optimal design for parallel test generation based on circuit partitioningFull-text access may be available. Sign in or learn about subscription options.pp. 297,298,299,300
by Dong Xiang, Dao-Zheng Wei
Data path testability evaluation via functional testability measuresFull-text access may be available. Sign in or learn about subscription options.pp. 301,302,303,304,305,306
by M. Jamoussi, B. Kaminska
An improved deductive fault simulatorFull-text access may be available. Sign in or learn about subscription options.pp. 307,308,309,310
by P.R. Sureshkumar, J. Jacob, M.K. Srinivas, V.D. Agrawal
On probabilistic testing of large-scale sequential circuits using circuit decompositionFull-text access may be available. Sign in or learn about subscription options.pp. 311,312,313,314
by S.R. Das, Wen-Ben Jone, A.R. Nayak, I. Choi
Low-cost redundancy identification for combinational circuitsFull-text access may be available. Sign in or learn about subscription options.pp. 315,316,317,318
by M.A. Iyer, M. Abramovici
Finite element analysis of SiGe npn HBTFull-text access may be available. Sign in or learn about subscription options.pp. 319,320,321,322
by G. Hari Rama Krishna, N.B. Chakrabarti, S. Banerjee
nOHM/spl minus/a multi-process device synthesis tool for lateral DMOS structuresFull-text access may be available. Sign in or learn about subscription options.pp. 323,324,325,326,327
by S. Natarajan, D. Sahu, S. Dasgupta
3D effects in VLSI/ULSI MOSFETs: a novel analytical approach to model threshold voltageFull-text access may be available. Sign in or learn about subscription options.pp. 328,329,330,331,332
by S.K. Lahiri, M.K. Das, A. Das Gupta, I. Manna
Parameterized modeling of open-circuit critical volume for three-dimensional defects in VLSI processingFull-text access may be available. Sign in or learn about subscription options.pp. 333,334,335,336,337,338
by M.R. Kidambi, A. Tyagi, M.R. Madani, M.A. Bayoumi
LATCHSIM/spl minus/a latch-up simulator in VLSI CAD environment for CMOS and BiCMOS circuitsFull-text access may be available. Sign in or learn about subscription options.pp. 339,340,341,342
by A. Bandyopadhyay, P.R. Verma, A.B. Bhattacharyya, M.J. Zarabi
A CORDIC based programmable DXT processor arrayFull-text access may be available. Sign in or learn about subscription options.pp. 343,344,345,346,347,348
by V.K. Anuradha, V. Visvanathan
Hierarchical reconfiguration of VLSI/WSI arraysFull-text access may be available. Sign in or learn about subscription options.pp. 349,350,351,352
by D. Bhatia, R. Rajagopalan, S. Katkoori
A linear systolic array for LU decompositionFull-text access may be available. Sign in or learn about subscription options.pp. 353,354,355,356,357,358
by E. Casseau, D. Degrugillier
An algorithm to test reconfigured RAMsFull-text access may be available. Sign in or learn about subscription options.pp. 359,360,361,362,363,364
by M. Franklin, K.K. Saluja
Response pipelined CAM chips: the first generation and beyondFull-text access may be available. Sign in or learn about subscription options.pp. 365,366,367,368
by K. Ghose, V.A. Dharmaraj
An integrated approach to state assignment and sequential element selection for FSM synthesisFull-text access may be available. Sign in or learn about subscription options.pp. 369,370,371,372
by M. Mehendale, B. Mitra
A new approach to synthesis of PLA-based FSM'sFull-text access may be available. Sign in or learn about subscription options.pp. 373,374,375,376,377,378
by C. Rama Mohan, P.P. Chakrabarti
Bitwise encoding of finite state machinesFull-text access may be available. Sign in or learn about subscription options.pp. 379,380,381,382
by J. Monteiro, J. Kukula, S. Devadas, H. Neto
Synthesis of initializable asynchronous circuitsFull-text access may be available. Sign in or learn about subscription options.pp. 383,384,385,386,387,388
by S.T. Chakradhar, S. Banerjee, R.K. Roy, D.K. Pradhan
Mechanical identification of inductive properties during verification of finite state machinesFull-text access may be available. Sign in or learn about subscription options.pp. 389,390,391,392,393,394
by I. Chakrabarti, D. Sarkar
Multiobjective search in VLSI designFull-text access may be available. Sign in or learn about subscription options.pp. 395,396,397,398,399,400
by P. Dasgupta, P. Mitra, P.P. Chakrabarti, S.C. DeSarkar
Graphical methodology language for CAD frameworksFull-text access may be available. Sign in or learn about subscription options.pp. 401,402,403,404,405,406
by J. Sienicki, M.L. Bushnell, S. Parikh
An object oriented environment for modeling and synthesis of hardware circuitsFull-text access may be available. Sign in or learn about subscription options.pp. 407,408,409,410,411,412
by S. Sarkar, A. Basu
Early exploration of the multi-dimensional VLSI design spaceFull-text access may be available. Sign in or learn about subscription options.pp. 413,414,415,416
by M.B. Takla, D.W. Bouldin, D.B. Koch
Verification of circuits described in VHDL through extraction of design intentFull-text access may be available. Sign in or learn about subscription options.pp. 417,418,419,420
by Y.V. Hoskote, J. Moondanos, J.A. Abraham, D.S. Fussell
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