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Eighth Workshop on Interaction between Compilers and Computer Architectures, 2004. INTERACT-8 2004.

Feb. 15 2004 to Feb. 15 2004

Madrid, Spain

ISBN: 0-7695-2061-8

Table of Contents

Proceedings Eighth Workshop on Interaction Between Compilers and Computer Architectures Copyright PageFreely available from IEEE.pp. iii-iii
Proceedings Eighth Workshop on Interaction Between Compilers and Computer ArchitecturesFreely available from IEEE.pp. iv-iv
Proceedings - Eighth Workshop on Interaction Between Compilers and Computer Architectures Table of ContentsFreely available from IEEE.pp. v-vi
Message From The Program ChairFreely available from IEEE.pp. vii-vii
by Wei C. Hsu
Introduction
Message from the Program ChairFreely available from IEEE.pp. vii
Introduction
Program CommitteeFreely available from IEEE.pp. viii
Session I. Loop Optimization
Continuous Trip Count Profiling for Loop Optimizations in Two-Phase Dynamic Binary TranslatorsFull-text access may be available. Sign in or learn about subscription options.pp. 3-12
by Youfeng Wu, Mauricio Breternitz, Tevi Devor
Session I. Loop Optimization
Exploitation of Instruction-Level Parallelism for Optimal Loop SchedulingFull-text access may be available. Sign in or learn about subscription options.pp. 13-21
by Jan M?, Dirk Fimmel, Renate Merker
Session II. Garbage Collection
Garbage Collector Refinement for New Dynamic Multimedia Applications on Embedded SystemsFull-text access may be available. Sign in or learn about subscription options.pp. 25-32
by Jose M. Velasco, David Atienza, Francky Catthoor, Francisco Tirado, Katzalin Olcoz, Jose M. Mendias
Session II. Garbage Collection
Dynamic Management of Nursery Space Organization in Generational CollectionFull-text access may be available. Sign in or learn about subscription options.pp. 33-40
by Jos? Manuel Velasco, Antonio Ortiz, Katzalin Olcoz, Francisco Tirado
Session III. Energy Efficient Computing
Cool-Fetch: A Compiler-Enabled IPC Estimation Based Framework for Energy ReductionFull-text access may be available. Sign in or learn about subscription options.pp. 43-52
by Osman S. Unsal, Israel Koren, C. Mani Krishna, Csaba Andras Moritz
Session III. Energy Efficient Computing
Energy-Efficiency Potential of a Phase-Based Cache Resizing Scheme for Embedded SystemsFull-text access may be available. Sign in or learn about subscription options.pp. 53-62
by Gilles Pokam, Fran?ois Bodin
Session IV. Fast Simulation and I-Cache
SimSnap: Fast-Forwarding via Native Execution and Application-Level CheckpointingFull-text access may be available. Sign in or learn about subscription options.pp. 65-74
by Peter K. Szwed, Daniel Marques, Robert M. Buels, Sally A. McKee, Martin Schulz
Session IV. Fast Simulation and I-Cache
Exploiting Procedure Level Locality to Reduce Instruction Cache MissesFull-text access may be available. Sign in or learn about subscription options.pp. 75-84
by Ravi V. Batchu, Daniel A. Jiménez
Session V. Branch Optimizations
Link-Time Optimization Techniques for Eliminating Conditional Branch RedundanciesFull-text access may be available. Sign in or learn about subscription options.pp. 87-96
by Manel Fernández, Roger Espasa
Session V. Branch Optimizations
Reducing Fetch Architecture Complexity Using Procedure InliningFull-text access may be available. Sign in or learn about subscription options.pp. 97-106
by Oliverio J. Santana, Alex Ramirez, Mateo Valero
Session VI. Data Cache Performance Optimization
Fast Indexing for Blocked Array Layouts to Improve Multi-Level Cache LocalityFull-text access may be available. Sign in or learn about subscription options.pp. 109-119
by Evangelia Athanasaki, Nectarios Koziris
Session VI. Data Cache Performance Optimization
Data Movement Optimization for Software-Controlled On-Chip MemoryFull-text access may be available. Sign in or learn about subscription options.pp. 120-127
by Motonobu Fujita, Masaaki Kondo, Hiroshi Nakamura
Author Index
Author IndexFreely available from IEEE.pp. 129
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