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On-Line Testing Workshop, IEEE International

July 8 2002 to July 10 2002

Isle of Bendor, France

ISBN: 0-7695-1641-6

Table of Contents

Proceedings of the Eighth IEEE International On-Line Testing Workshop (IOLTW 2002)Freely available from IEEE.
Introduction
Message from the Conference ChairsFreely available from IEEE.pp. xii
Introduction
Conference OrganizationFreely available from IEEE.pp. xiii
Introduction
TTTC InformationFull-text access may be available. Sign in or learn about subscription options.pp. 271
Session 1: Hardware Fault Tolerance
An Architecture for Self-Healing Digital SystemsFull-text access may be available. Sign in or learn about subscription options.pp. 3
by P. K. Lala, B. Kiran Kumar
Session 1: Hardware Fault Tolerance
Coding Scheme for Low Energy Consumption Fault-Tolerant BusFull-text access may be available. Sign in or learn about subscription options.pp. 8
by D. Rossi, V. E. S. van Dijk, R. P. Kleihorst, A. H. Nieuwland, C. Metra
Session 1: Hardware Fault Tolerance
Survivable Discrete Circuits DesignFull-text access may be available. Sign in or learn about subscription options.pp. 13
by A. Matrosova, V. Andreeva, Yu. Sedov
Session 2: Hardware-Software Design and Validation of Fault Tolerant Systems
Fault Tolerance Evaluation Using Two Software Based Fault Injection MethodsFull-text access may be available. Sign in or learn about subscription options.pp. 21
by Astrit Ademaj, Petr Grillinger, Pavel Herout, Jan Hlavicka
Session 2: Hardware-Software Design and Validation of Fault Tolerant Systems
Automated Synthesis of SEU Tolerant Architectures from OO DescriptionsFull-text access may be available. Sign in or learn about subscription options.pp. 26
by S. Chiusano, S. DiI Carlo, P. Prinetto
Session 2: Hardware-Software Design and Validation of Fault Tolerant Systems
A System Level Approach in Designing Dual-Duplex Fault Tolerant Embedded SystemsFull-text access may be available. Sign in or learn about subscription options.pp. 32
by C. Bolchini, L. Pomante, F. Salice, D. Sciuto
Session 3: Self Checking Circuits
A New Self-Checking Code-Disjoint Carry-Skip AdderFull-text access may be available. Sign in or learn about subscription options.pp. 39
by D. Marienfeld, E. S. Sogomonyan, V. Ocheretnij, M. Gössel
Session 3: Self Checking Circuits
Sequential Circuits Applicable for Detecting Different Types of FaultsFull-text access may be available. Sign in or learn about subscription options.pp. 44
by I. Levin, V. Sinelnikov, M. Karpovsky, S. Ostanin
Session 4: Concurrent Error Detection I
A High Speed Encoder for Recursive Systematic Convolutive CodesFull-text access may be available. Sign in or learn about subscription options.pp. 51
by A. M?sir, F. Monteiro, A. Dandache, B. Lepley
Session 4: Concurrent Error Detection I
A Hierarchical Architecture for Concurrent Soft Error Detection Based on Current SensingFull-text access may be available. Sign in or learn about subscription options.pp. 56
by Y. Tsiatouhas, A. Arapoyanni, D. Nikolos, Th. Haniotakis
Session 4: Concurrent Error Detection I
Design of Real-Number Checksum Codes Using Shared Partial Computation for CED in Linear DSP SystemsFull-text access may be available. Sign in or learn about subscription options.pp. 61
by Huy Nguyen, Abhijit Chatterjee
Session 5: Concurrent Error Detection II
On-Line Error Detection and Correction in Storage Elements with Cross-Parity CheckFull-text access may be available. Sign in or learn about subscription options.pp. 69
by M. Pflanz, K. Walther, C. Galke, H. T. Vierhaus
Session 5: Concurrent Error Detection II
On-Line Monitor Design of Finite-State MachinesFull-text access may be available. Sign in or learn about subscription options.pp. 74
by Feng Gao, John P. Hayes
Session 5: Concurrent Error Detection II
A Statistical Sampler for a New On-line Analog Test MethodFull-text access may be available. Sign in or learn about subscription options.pp. 79
by M. Negreiros, L. Carro, A. A. Susin
Session 6: Analog and Mixed Signal Testing and Reliability
A ΣΔ A/D Converter Insensitive to SEU EffectsFull-text access may be available. Sign in or learn about subscription options.pp. null
by Fernando Paixão Cortes, Luigi Carro, Alessandro Girardi, Altamiro Suzim
Session 6: Analog and Mixed Signal Testing and Reliability
A BICS for CMOS Opamps by Monitoring the Supply Current PeakFull-text access may be available. Sign in or learn about subscription options.pp. 94
by J. Font, J. Ginard, E. Isern, M. Roca, J. Segura, E. García
Session 6: Analog and Mixed Signal Testing and Reliability
Analog Switches in Programmable Analog Devices: Quiescent Defective BehavioursFull-text access may be available. Sign in or learn about subscription options.pp. 99
by R. Rodríguez-Montañés, D. Muñoz, L. Balado, J. Figueras
Session 7: Fault Injection Techniques and Results
Multi-Level Fault Injection Experiments Based on VHDL Descriptions: A Case StudyFull-text access may be available. Sign in or learn about subscription options.pp. 107
by R. Leveugle, K. Hadjiat
Analysis of SEU effects in a pipelined processorFull-text access may be available. Sign in or learn about subscription options.pp. 112-116
by M. Rebaudengo, M. Sonza Reorda, M. Violante
Session 7: Fault Injection Techniques and Results
Bit Flip Injection in Processor-Based Architectures: A Case StudyFull-text access may be available. Sign in or learn about subscription options.pp. 117
by G. C. Cardarilli, F. Kaddour, A. Leandri, M. Ottavi, S. Pontarelli, R. Velazco
Session 8: BIST Techniques I
BIST-Based Delay-Fault Testing in FPGAsFull-text access may be available. Sign in or learn about subscription options.pp. 131
by Miron Abramovici, Charles Stroud
Session 8: BIST Techniques I
Built-In-Self-Test of Analogue Circuits Using Optimised Fault Sets and Transient Response TestingFull-text access may be available. Sign in or learn about subscription options.pp. 135
by N. Axelos, J. Watson, D. Taylor, A. Platts
Session 8: BIST Techniques I
A Low Power Pseudo-Random BIST TechniqueFull-text access may be available. Sign in or learn about subscription options.pp. 140
by Nadir Z. Basturkmen, Sudhakar M. Reddy, Irith Pomeranz
Session 9: BIST Techniques II
Stop & Go BISTFull-text access may be available. Sign in or learn about subscription options.pp. 147
by Ilia Polian, Bernd Becker
Session 9: BIST Techniques II
Bit-Serial Test Pattern Generation by an Accumulator Behaving as a Non-Linear Feedback Shift RegisterFull-text access may be available. Sign in or learn about subscription options.pp. 152
by G. Dimitrakopoulos, D. Nikolos, D. Bakalis
Session 9: BIST Techniques II
Built-in Generation of m -Sequences with Irreducible Characteristic PolynomialsFull-text access may be available. Sign in or learn about subscription options.pp. 158
by Dimitri Kagaris
Session 10: Testing Issues
Active Replication: Towards a Truly SRAM-Based FPGA On-Line Concurrent TestingFull-text access may be available. Sign in or learn about subscription options.pp. 165
by Manuel G. Gericota, Gustavo R. Alves, Miguel L. Silva, José M. Ferreira
Session 10: Testing Issues
Checkers for RF Matching Networks on an Automatic Test BoardFull-text access may be available. Sign in or learn about subscription options.pp. 170
by Giuseppe Di Gregorio, Maria Grazia La Rosa, Biagio Russo
Session 11: Posters
Adaptive IDDQ: How to Set an IDDQ Limit for any Device Under TestFull-text access may be available. Sign in or learn about subscription options.pp. 177
by Carlo Dallavalle
Session 11: Posters
On-line Detection and Compensation of Transient Errors in Processor Pipeline-StructuresFull-text access may be available. Sign in or learn about subscription options.pp. 178
by C. Galke, M. Pflanz, H. T. Vierhaus
Session 11: Posters
Recovering Sequential Circuits from Temporary Faults: The Survival Capability of Scan-CellsFull-text access may be available. Sign in or learn about subscription options.pp. 179
by Jose Miguel Vieira dos Santos
Session 11: Posters
Learning-Based On-Line Testing in Feedforward Neural NetworksFull-text access may be available. Sign in or learn about subscription options.pp. 180
by Naotake Kamiura, Kazuharu Yamato, Teijiro Isokawa, Nobuyuki Matsui
Session 11: Posters
On-Line Detection of Short Circuits in Digital Devices and SystemsFull-text access may be available. Sign in or learn about subscription options.pp. 183
by Adam Kristof
Session 11: Posters
Using Concurrent and Semi-Concurrent On-Line Testing During HLS: An Adaptable ApproachFull-text access may be available. Sign in or learn about subscription options.pp. 184
by M. A. Naal, M. Rakotoar, E. Simeu, C. Aktouf
Session 11: Posters
Transformation Based Insertion of On-Line Testing Resources in a High-Level Synthesis EnvironmentFull-text access may be available. Sign in or learn about subscription options.pp. 185
by Petros Oikonomakos, Mark Zwolinski
Session 11: Posters
Robust Data Compression for Analogue Test OutputsFull-text access may be available. Sign in or learn about subscription options.pp. 186
by Aleksandra Rankov, Gaynor E. Taylor, John Webster
Session 11: Posters
A New On-Line Robust Approach to Design Noise Immune Speech Recognition SystemsFull-text access may be available. Sign in or learn about subscription options.pp. 187
by F. Vargas, R. D. Fagundes, D. Barros Jr.
Session 11: Posters
Radiation Effects Facility RADEFFull-text access may be available. Sign in or learn about subscription options.pp. 188
by Ari Virtanen
Session 11: Posters
Sequential n -Detection Criteria: Keep It Simple!Full-text access may be available. Sign in or learn about subscription options.pp. 189
by Ilia Polian, Martin Keim, Nicolai Mallig, Bernd Becker
Session 11: Posters
On-line Testing of Embedded Systems Using Optical Probes: System Modeling and Probing TechnologyFull-text access may be available. Sign in or learn about subscription options.pp. 191
by Chouki Aktouf, Benoît Pannetier, Pierre Lemaître- Auger, Smail Tedjini
Session 11: Posters
An Off-Chip Sensor Circuit for On-Line Transient Current TestingFull-text access may be available. Sign in or learn about subscription options.pp. 192
by B. Alorda, A. Ivanov, J. Segura
Session 11: Posters
Analysis of the Equivalences and Dominances of Transient Faults at the RT LevelFull-text access may be available. Sign in or learn about subscription options.pp. 193
by Luis Berrojo, Isabel González, Luis Entrena, Celia López, Fulvio Corno, Matteo Sonza, Giovanni Squillero
Session 11: Posters
Injecting Multiple Upsets in a SEU Tolerant 8051 Micro-ControllerFull-text access may be available. Sign in or learn about subscription options.pp. 194
by F. Lima, L. Carro, R. Velazco, R. Reis
Session 11: Posters
Error Rate Estimation for a Flight Application Using the CEU Fault Injection ApproachFull-text access may be available. Sign in or learn about subscription options.pp. 195
by F. Kaddour, S. Rezgui, R. Velazco, S. Rodriguez, J. R. De Mingo
Session 12: Memory BIST Analysis and Application
Defect-Oriented Analysis of Memory BIST TestsFull-text access may be available. Sign in or learn about subscription options.pp. 201
by Alvin Jee
A BIST-based solution for the diagnosis of embedded memories adopting image processing techniquesFull-text access may be available. Sign in or learn about subscription options.pp. 206-210
by D. Appello, A. Fudoli, V. Tancorre, F. Corno, M. Rebaudengo, M. Sonza Reorda
Session 12: Memory BIST Analysis and Application
A Scan-Bist Environment for Testing Embedded MemoriesFull-text access may be available. Sign in or learn about subscription options.pp. 211
by F. Karimi, F. Lombardi
Session 13: Memory ECC and Soft Errors
Fast and Compact Error Correcting Scheme for Reliable Multilevel Flash MemoriesFull-text access may be available. Sign in or learn about subscription options.pp. 221
by D. Rossi, C. Metra, B. Riccò
Session 13: Memory ECC and Soft Errors
High Speed 15 ns 4 Mbits SRAM for Space ApplicationFull-text access may be available. Sign in or learn about subscription options.pp. 226
by Bernard Coloma, Patrick Delaunay, Olivier Husson
Session 14: High Reliability in Railway and Automotive Systems
The YATE Fail-Safe Interface: The User?s Point of ViewFull-text access may be available. Sign in or learn about subscription options.pp. 233
by D. Bied-Charreton, D. Guillon, B. Jacques
Session 14: High Reliability in Railway and Automotive Systems
Fault Tolerant Insertion and Verification: A Case StudyFull-text access may be available. Sign in or learn about subscription options.pp. 238
by Alberto Manzone, Diego De Costantini
Session 14: High Reliability in Railway and Automotive Systems
Design and Implementation of a Self-Checking Scheme for Railway Trackside SystemsFull-text access may be available. Sign in or learn about subscription options.pp. 243
by Luca Schiano, Cecilia Metra, Diego Marino
Session 15: Embedded Memory Yield Enhancement
A Silicon-Based Yiel Gain Evaluation Methodology for Embedded-SRAMs with Different Redundancy ScenariosFull-text access may be available. Sign in or learn about subscription options.pp. 251
by E. Rondey, Y. Tellier, S. Borri
Session 15: Embedded Memory Yield Enhancement
A March-Based Fault Location Algorithm for Static Random Access MemoriesFull-text access may be available. Sign in or learn about subscription options.pp. 256
by V. A. Vardanian, Y. Zorian
Session 15: Embedded Memory Yield Enhancement
A Simulator for E aluating Redundancy Analysis Algorithms of Repairable Embedded MemoriesFull-text access may be available. Sign in or learn about subscription options.pp. 262
by Rei-Fu Huang, Jin-Fu Li, Jen-Chieh Yeh, Cheng-Wen Wu
Author Index
Author IndexFreely available from IEEE.pp. 269
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