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Proceedings of 21 International Symposium on Computer Architecture

April 18 1994 to April 21 1994

Chicago, IL, USA

Table of Contents

Decoupled sectored caches: conciliating low tag implementation cost and low miss ratioFull-text access may be available. Sign in or learn about subscription options.pp. 384,385,386,387,388,389,390,391,392,393
by A. Seznec
Expected I-cache miss rates via the gap modelFull-text access may be available. Sign in or learn about subscription options.pp. 372,373,374,375,376,377,378,379,380,381,382,383
by R.W. Quong
Optimal allocation of on-chip memory for multiple-API operating systemsFull-text access may be available. Sign in or learn about subscription options.pp. 358,359,360,361,362,363,364,365,366,367,368,369
by D. Nagle, R. Uhlig, T. Mudge, S. Sechrest
A unified architectural tradeoff methodologyFull-text access may be available. Sign in or learn about subscription options.pp. 348,349,350,351,352,353,354,355,356,357
by Chung-Ho Chen, A.K. Somani
A study of single-chip processor/cache organizations for large numbers of transistorsFull-text access may be available. Sign in or learn about subscription options.pp. 338,339,340,341,342,343,344,345,346,347
by M. Farrens, G. Tyson, A.R. Pleszkun
Tempest and Typhoon: user-level shared memoryFull-text access may be available. Sign in or learn about subscription options.pp. 325,326,327,328,329,330,331,332,333,334,335,336
by S.K. Reinhardt, J.R. Larus, D.A. Wood
Software-extended coherent shared memory: performance and costFull-text access may be available. Sign in or learn about subscription options.pp. 314,315,316,317,318,319,320,321,322,323,324
by D. Chaiken, A. Agarwal
The Stanford FLASH multiprocessorFull-text access may be available. Sign in or learn about subscription options.pp. 302,303,304,305,306,307,308,309,310,311,312,313
by J. Kuskin, D. Ofelt, M. Heinrich, J. Heinlein, R. Simoni, K. Gharachorloo, J. Chapin, D. Nakahira, J. Baxter, M. Horowitz, A. Gupta, M. Rosenblum, J. Hennessy
Compressionless Routing: a framework for adaptive and fault-tolerant routingFull-text access may be available. Sign in or learn about subscription options.pp. 289,290,291,292,293,294,295,296,297,298,299,300
by J.H. Kim, Ziqiang Liu, A.A. Chien
Ariadne/spl minus/an adaptive router for fault-tolerant multicomputersFull-text access may be available. Sign in or learn about subscription options.pp. 278,279,280,281,282,283,284,285,286,287,288
by J.D. Allen, P.T. Gaughan, D.E. Schimmel, S. Yalamanchili
METRO: a router architecture for high-performance, short-haul routing networksFull-text access may be available. Sign in or learn about subscription options.pp. 266,267,268,269,270,271,272,273,274,275,276,277
by A. DeHon, F. Chong, M. Becker, E. Egozy, H. Minsky, S. Peretz, T.F. Knight
Crosshatch disk array for improved reliability and performanceFull-text access may be available. Sign in or learn about subscription options.pp. 255,256,257,258,259,260,261,262,263,264
by S.W. Ng
EVENODD: an optimal scheme for tolerating double disk failures in RAID architecturesFull-text access may be available. Sign in or learn about subscription options.pp. 245,246,247,248,249,250,251,252,253,254
by M. Blaum, J. Brady, J. Bruck, J. Menon
RAID-II: a high-bandwidth network file serverFull-text access may be available. Sign in or learn about subscription options.pp. 234,235,236,237,238,239,240,241,242,243,244
by A.L. Drapeau, K.W. Shirriff, J.H. Hartman, E.L. Miller, S. Seshan, R.H. Katz, K. Lutz, D.A. Patterson, E.K. Lee, P.M. Chen, G.A. Gibson
A performance study of software and hardware data prefetching schemesFull-text access may be available. Sign in or learn about subscription options.pp. 223,224,225,226,227,228,229,230,231,232
by Tien-Fu Chen, J.-L. Baer
Complexity/performance tradeoffs with non-blocking loadsFull-text access may be available. Sign in or learn about subscription options.pp. 211,212,213,214,215,216,217,218,219,220,221,222
by K.I. Farkas, N.P. Jouppi
Speculative disambiguation: a compilation technique for dynamic memory disambiguationFull-text access may be available. Sign in or learn about subscription options.pp. 200,201,202,203,204,205,206,207,208,209,210
by A.S. Huang, G. Slavenburg, J.P. Shen
Combined performance gains of simple cache protocol extensionsFull-text access may be available. Sign in or learn about subscription options.pp. 187,188,189,190,191,192,193,194,195,196,197
by F. Dahlgren, M. Dubois, P. Stenstrom
Impact of sharing-based thread placement on multithreaded architecturesFull-text access may be available. Sign in or learn about subscription options.pp. 176,177,178,179,180,181,182,183,184,185,186
by R. Thekkath, S.J. Eggers
Exploring the design space for a shared-cache multiprocessorFull-text access may be available. Sign in or learn about subscription options.pp. 166,167,168,169,170,171,172,173,174,175
by B.A. Nayfeh, K. Olukotun
Architecture and evaluation of a high-speed networking subsystem for distributed-memory systemsFull-text access may be available. Sign in or learn about subscription options.pp. 154,155,156,157,158,159,160,161,162,163
by P. Steenkiste, M. Hemy, T. Mummert, B. Zill
Virtual memory mapped network interface for the SHRIMP multicomputerFull-text access may be available. Sign in or learn about subscription options.pp. 142,143,144,145,146,147,148,149,150,151,152,153
by M.A. Blumrich, Kai Li, R. Alpert, C. Dubnicki, E.W. Felten, J. Sandberg
Branch with masked squashing in superpipelined processorsFull-text access may be available. Sign in or learn about subscription options.pp. 130,131,132,133,134,135,136,137,138,139,140
by Ching-Long Su, A.M. Despain
Guarded execution and branch prediction in dynamic ILP processorsFull-text access may be available. Sign in or learn about subscription options.pp. 120,121,122,123,124,125,126,127,128,129
by D.N. Pnevmatikatos, G.S. Sohi
Software versus hardware shared-memory implementation: a case studyFull-text access may be available. Sign in or learn about subscription options.pp. 106,107,108,109,110,111,112,113,114,115,116,117
by A.L. Cox, S. Dwarkadas, P. Keleher, Honghui Lu, R. Rajamony, W. Zwaenepoel
A comparison of message passing and shared memory architectures for data parallel programsFull-text access may be available. Sign in or learn about subscription options.pp. 94,95,96,97,98,99,100,101,102,103,104,105
by A.C. Klaiber, H.M. Levy
Evaluating the memory overhead required for COMA architecturesFull-text access may be available. Sign in or learn about subscription options.pp. 82,83,84,85,86,87,88,89,90,91,92,93
by T. Joe, J.L. Hennessy
Measurement-based characterization of global memory and network contention, operating system and parallelisation overheads: case study on a shared-memory multiprocessorFull-text access may be available. Sign in or learn about subscription options.pp. 71,72,73,74,75,76,77,78,79,80
by C. Natarajan, S. Sharma, R.K. Iyer
Characterization of Alpha AXP performance using TP and SPEC workloadsFull-text access may be available. Sign in or learn about subscription options.pp. 60,61,62,63,64,65,66,67,68,69,70
by Z. Cvetanovic, D. Bhandarkar
Architectural support for performance tuning: a case study on the SPARCcenter 2000Full-text access may be available. Sign in or learn about subscription options.pp. 48,49,50,51,52,53,54,55,56,57,58,59
by A. Singhal, A.J. Goldberg
Tradeoffs in two-level on-chip cachingFull-text access may be available. Sign in or learn about subscription options.pp. 34,35,36,37,38,39,40,41,42,43,44,45
by N.P. Jouppi, S.J.E. Wilton
Evaluating stream buffers as a secondary cache replacementFull-text access may be available. Sign in or learn about subscription options.pp. 24,25,26,27,28,29,30,31,32,33
by S. Palacharla, R.E. Kessler
The impact of unresolved branches on branch prediction scheme performanceFull-text access may be available. Sign in or learn about subscription options.pp. 12,13,14,15,16,17,18,19,20,21
by A.R. Talcott, W. Yamamoto, M.J. Serrano, R.C. Wood, M. Nemirovsky
Fast and accurate instruction fetch and branch predictionFull-text access may be available. Sign in or learn about subscription options.pp. 2,3,4,5,6,7,8,9,10,11
by B. Calder, D. Grunwald
Proceedings of 21 International Symposium on Computer ArchitectureFreely available from IEEE.pp. 0_1-0_1
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