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Computer Architecture, International Symposium on

June 9 2003 to June 11 2003

San Diego, California

ISSN: 1063-6897

ISBN: 0-7695-1945-8

Table of Contents

Proceedings 30th Annual International Symposium on Computer ArchitectureFull-text access may be available. Sign in or learn about subscription options.
A "flight data recorder" for enabling full-system multiprocessor deterministic replayFull-text access may be available. Sign in or learn about subscription options.pp. 122,123,124,125,126,127,128,129,130,131,132,133
by M. Xu, R. Bodik, M.D. Hill
Symposium Chairman's WelcomeFreely available from IEEE.pp. ix
Message from the Program ChairFreely available from IEEE.pp. x
Committee MembersFreely available from IEEE.pp. xi
Session 1: Thermal and Energy-Aware Microarchitectures
Temperature-Aware MicroarchitectureFull-text access may be available. Sign in or learn about subscription options.pp. 2
by Kevin Skadron, Mircea R. Stan, Wei Huang, Sivakumar Velusamy, Karthik Sankaranarayanan, David Tarjan
Session 1: Thermal and Energy-Aware Microarchitectures
Profile-based Dynamic Voltage and Frequency Scaling for a Multiple Clock Domain MicroprocessorFull-text access may be available. Sign in or learn about subscription options.pp. 14
by Grigorios Magklis, Michael L. Scott, Greg Semeraro, David H. Albonesi, Steven Dropsho
Session 2: Processor Architecture
Half-Price ArchitectureFull-text access may be available. Sign in or learn about subscription options.pp. 28
by Ilhyun Kim, Mikko H. Lipasti
Session 2: Processor Architecture
Implicitly-Multithreaded ProcessorsFull-text access may be available. Sign in or learn about subscription options.pp. 39
by Il Park, Babak Falsafi, T. N. Vijaykumar
Panel: Subsetting SPEC When Measuring Results: Valid or Manipulative?
MisSPECulation: Partial and Misleading Use of SPEC CPU2000 in Computer Architecture ConferencesFull-text access may be available. Sign in or learn about subscription options.pp. 52
by Daniel Citron
Session 3a: Microarchitecture Techniques
Banked Multiported Register Files for High-Frequency Superscalar MicroprocessorsFull-text access may be available. Sign in or learn about subscription options.pp. 62
by Jessica H. Tseng, Krste Asanovic
Session 3a: Microarchitecture Techniques
Pipeline Damping: A Microarchitectural Technique to Reduce Inductive Noise in Supply VoltageFull-text access may be available. Sign in or learn about subscription options.pp. 72
by Michael D. Powell, T. N. Vijaykumar
Session 3a: Microarchitecture Techniques
SMARTS: Accelerating Microarchitecture Simulation via Rigorous Statistical SamplingFull-text access may be available. Sign in or learn about subscription options.pp. 84
by Roland E. Wunderlich, Thomas F. Wenisch, Babak Falsafi, James C. Hoe
Session 3b: Recovery and Replay
Transient-Fault Recovery for Chip MultiprocessorsFull-text access may be available. Sign in or learn about subscription options.pp. 98
by Mohamed Gomaa, Chad Scarbrough, T. N. Vijaykumar, Irith Pomeranz
Session 3b: Recovery and Replay
ReEnact: Using Thread-Level Speculation Mechanisms to Debug Data Races in Multithreaded CodesFull-text access may be available. Sign in or learn about subscription options.pp. 110
by Milos Prvulovic, Josep Torrellas
Session 3b: Recovery and Replay
A "Flight Data Recorder" for Enabling Full-system Multiprocessor Deterministic ReplayFull-text access may be available. Sign in or learn about subscription options.pp. 122
by Min Xu, Rastislav Bodik, Mark D. Hill
Session 4a: Energy-Saving Designs
A Highly Configurable Cache Architecture for Embedded SystemsFull-text access may be available. Sign in or learn about subscription options.pp. 136
by Chuanjun Zhang, Frank Vahid, Walid Najjar
Session 4a: Energy-Saving Designs
Energy Efficient Co-Adaptive Instruction Fetch and IssueFull-text access may be available. Sign in or learn about subscription options.pp. 147
by Alper Buyuktosunoglu, Tejas Karkhanis, David H. Albonesi, Pradip Bose
Session 4a: Energy-Saving Designs
Positional Adaptation of Processors: Application to Energy ReductionFull-text access may be available. Sign in or learn about subscription options.pp. 157
by Michael C. Huang, Jose Renau, Josep Torrellas
Session 4a: Energy-Saving Designs
DRPM: Dynamic Speed Control for Power Management in Server Class DisksFull-text access may be available. Sign in or learn about subscription options.pp. 169
by Sudhanva Gurumurthi, Anand Sivasubramaniam, Mahmut Kandemir, Hubertus Franke
Session 4b: Interconnects and Multiprocessors
Token Coherence: Decoupling Performance and CorrectnessFull-text access may be available. Sign in or learn about subscription options.pp. 182
by Milo M. K. Martin, Mark D. Hill, David A. Wood
Session 4b: Interconnects and Multiprocessors
GOAL: A Load-Balanced Adaptive Routing Algorithm for Torus NetworksFull-text access may be available. Sign in or learn about subscription options.pp. 194
by Arjun Singh, William J Dally, Amit K Gupta, Brian Towles
Session 4b: Interconnects and Multiprocessors
Using Destination-Set Prediction to Improve the Latency/Bandwidth Tradeoff in Shared-Memory MultiprocessorsFull-text access may be available. Sign in or learn about subscription options.pp. 206
by Milo M. K. Martin, Pacia J. Harper, Daniel J. Sorin, Mark D. Hill, David A. Wood
Author indexFreely available from IEEE.pp. 447-448
Session 4b: Interconnects and Multiprocessors
Performance Analysis of the Alpha 21364-based HP GS1280 MultiprocessorFull-text access may be available. Sign in or learn about subscription options.pp. 218
by Zarka Cvetanovic
Session 5: Front-End Scheduling
Parallelism in the Front-EndFull-text access may be available. Sign in or learn about subscription options.pp. 230
by Paramjit S. Oberoi, Gurindar S. Sohi
Session 5: Front-End Scheduling
Effective ahead pipelining of instruction block address generationFull-text access may be available. Sign in or learn about subscription options.pp. 241
by Andr? Seznec, Antony Fraboulet
Session 5: Front-End Scheduling
Cyclone: A Broadcast-Free Dynamic Instruction Scheduler with Selective ReplayFull-text access may be available. Sign in or learn about subscription options.pp. 253
by Dan Ernst, Andrew Hamel, Todd Austin
Session 6a: Clustered Processors
Improving Dynamic Cluster Assignment for Clustered Trace Cache ProcessorsFull-text access may be available. Sign in or learn about subscription options.pp. 264
by Ravi Bhargava, Lizy K. John
Session 6a: Clustered Processors
Dynamically Managing the Communication-Parallelism Trade-off in Future Clustered ProcessorsFull-text access may be available. Sign in or learn about subscription options.pp. 275
by Rajeev Balasubramonian, Sandhya Dwarkadas, David H. Albonesi
Session 6b: Network Processors
A Pipelined Memory Architecture for High Throughput Network ProcessorsFull-text access may be available. Sign in or learn about subscription options.pp. 288
by Timothy Sherwood, George Varghese, Brad Calder
Session 6b: Network Processors
Efficient Use of Memory Bandwidth to Improve Network Processor ThroughputFull-text access may be available. Sign in or learn about subscription options.pp. 300
by Jahangir Hasan, Satish Chandra, T. N. Vijaykumar
Session 7a: Prediction
Improving Branch Prediction by Dynamic Dataflow-based Identification of Correlated Branches from a Large Global HistoryFull-text access may be available. Sign in or learn about subscription options.pp. 314
by Renju Thomas, Manoj Franklin, Chris Wilkerson, Jared Stark
Session 7a: Prediction
Detecting Global Stride Locality in Value StreamsFull-text access may be available. Sign in or learn about subscription options.pp. 324
by Huiyang Zhou, Jill Flanagan, Thomas M. Conte
Session 7a: Prediction
Phase Tracking and PredictionFull-text access may be available. Sign in or learn about subscription options.pp. 336
by Timothy Sherwood, Suleyman Sair, Brad Calder
Session 7b: Mechanisms and Support
Virtual Simple Architecture (VISA): Exceeding the Complexity Limit in Safe Real-Time SystemsFull-text access may be available. Sign in or learn about subscription options.pp. 350
by Aravindh Anantaraman, Kiran Seth, Kaustubh Patil, Eric Rotenberg, Frank Mueller
Session 7b: Mechanisms and Support
DISE: A Programmable Macro Engine for Customizing ApplicationsFull-text access may be available. Sign in or learn about subscription options.pp. 362
by Marc L. Corliss, E Christopher Lewis, Amir Roth
Session 7b: Mechanisms and Support
Building Quantum Wires: The Long and the Short of itFull-text access may be available. Sign in or learn about subscription options.pp. 374
by Mark Oskin, Frederic T. Chong, Isaac L. Chuang, John Kubiatowicz
Session 8: Memory Issues
Guided Region Prefetching: A Cooperative Hardware/Software ApproachFull-text access may be available. Sign in or learn about subscription options.pp. 388
by Zhenlin Wang, Doug Burger, Kathryn S. McKinley, Steven K. Reinhardt, Charles C. Weems
Session 8: Memory Issues
Overcoming the Limitations of Conventional Vector ProcessorsFull-text access may be available. Sign in or learn about subscription options.pp. 399
by Christos Kozyrakis, David Patterson
Session 8: Memory Issues
A Performance Analysis of PIM, Stream Processing, and Tiled Processing on Memory-Intensive Signal Processing KernelsFull-text access may be available. Sign in or learn about subscription options.pp. 410
by Jinwoo Suh, Eun-Gyu Kim, Stephen P. Crago, Lakshmi Srinivasan, Matthew C. French
Session 9: Exploiting Parallelisms
Exploiting ILP, TLP, and DLP with the Polymorphous TRIPS ArchitectureFull-text access may be available. Sign in or learn about subscription options.pp. 422
by Karthikeyan Sankaralingam, Ramadass Nagarajan, Haiming Liu, Changkyu Kim, Jaehyuk Huh, Doug Burger, Stephen W. Keckler, Charles R. Moore
Session 9: Exploiting Parallelisms
The Jrpm System for Dynamically Parallelizing Java ProgramsFull-text access may be available. Sign in or learn about subscription options.pp. 434
by Michael K. Chen, Kunle Olukotun
Session 9: Exploiting Parallelisms
Author's IndexFreely available from IEEE.pp. 447
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