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Proceedings
ISLPED
ISLPED 2007
Generate Citations
Low Power Electronics and Design, International Symposium on
Aug. 27 2007 to Aug. 29 2007
Portland, OR, USA
ISBN: 978-1-59593-709-4
Table of Contents
Papers
Nanotechnology for low-power and high-speed nanoelectronics applications
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pp. 1-1
by
Robert Chau
Papers
Compact modeling of carbon nanotube transistor for early stage process-design exploration
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pp. 2-7
by
Asha Balijepalli
,
Saurabh Sinha
,
Yu Cao
Papers
A floating-body dynamic supply boosting technique for low-voltage sram in nanoscale PD/SOI CMOS technologies
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pp. 8-13
by
Rajiv Joshi
,
Rouwaida Kanj
,
Keunwoo Kim
,
Richard Williams
,
Ching-Te Chuang
Papers
Low power FPGA design using hybrid CMOS-NEMS approach
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pp. 14-19
by
Yu Zhou
,
Shijo Thekkel
,
Swarup Bhunia
Papers
Design and analysis of Thin-BOX FD/SOI devices for low-power and stable SRAM in sub-50nm technologies
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pp. 20-25
by
Saibal Mukhopadhyay
,
Keunwoo Kim
,
Ching-Te Chuang
Papers
Clocking structures and power analysis for nanomagnet-based logic devices
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pp. 26-31
by
M. Niemier
,
M. Alam
,
X. S. Hu
,
G. Bernstein
,
W. Porod
,
M. Putney
,
J. DeAngelis
Papers
Energy efficient near-threshold chip multi-processing
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pp. 32-37
by
Bo Zhai
,
Ronald G. Dreslinski
,
David Blaauw
,
Trevor Mudge
,
Dennis Sylvester
Papers
Analysis of dynamic voltage/frequency scaling in chip-multiprocessors
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pp. 38-43
by
Sebastian Herbert
,
Diana Marculescu
Papers
Evaluating design tradeoffs in on-chip power management for CMPs
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pp. 44-49
by
Joseph Sharkey
,
Alper Buyuktosunoglu
,
Pradip Bose
Papers
Impact of die-to-die and within-die parameter variations on the throughput distribution of multi-core processors
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pp. 50-55
by
Keith A. Bowman
,
Alaa R. Alameldeen
,
Srikanth T. Srinivasan
,
Chris B. Wilkerson
Papers
A reusability-aware cache memory sharing technique for high-performance low-power CMPs with private L2 caches
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pp. 56-61
by
Sungjune Youn
,
Hyunhee Kim
,
Jihong Kim
Papers
Dual signal frequencies and voltage levels for low power and temperature-gradient tolerant clock distribution
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pp. 62-67
by
Sherif A. Tawfik
,
Volkan Kursun
Papers
A robust edge encoding technique for energy-efficient multi-cycle interconnect
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pp. 68-73
by
Jae-sun Seo
,
Dennis Sylvester
,
David Blaauw
,
Himanshu Kaul
,
Ram Krishnamurthy
Papers
Low-power process-variation tolerant arithmetic units using input-based elastic clocking
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pp. 74-79
by
Debabrata Mohapatra
,
Georgios Karakonstantis
,
Kaushik Roy
Papers
Sleep transistor sizing and control for resonant supply noise damping
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pp. 80-85
by
Jie Gu
,
Hanyong Eom
,
Chris H. Kim
Papers
Thermal-aware methodology for repeater insertion in low-power VLSI circuits
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pp. 86-91
by
Ja Chun Ku
,
Yehea Ismail
Papers
Post-placement leakage optimization for partially dynamically reconfigurable FPGAs
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pp. 92-97
by
Chi-Feng Li
,
Ping-Hung Yuh
,
Chia-Lin Yang
,
Yao-Wen Chang
Papers
Power optimal MTCMOS repeater insertion for global buses
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pp. 98-103
by
Hanif Fatemi
,
Behnam Amelifar
,
Massoud Pedram
Papers
Timing-driven row-based power gating
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pp. 104-109
by
Ashoka Sathanur
,
Antonio Pullini
,
Luca Benini
,
Alberto Macii
,
Enrico Macii
,
Massimo Poncino
Papers
Detailed placement for leakage reduction using systematic through-pitch variation
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pp. 110-115
by
Andrew B. Kahng
,
Swamy Muddu
,
Puneet Sharma
Papers
Early power grid verification under circuit current uncertainties
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pp. 116-121
by
Imad A. Ferzli
,
Farid N. Najm
,
Lars Kruse
Papers
Future of on-chip interconnection architectures
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pp. 122-122
by
Shekhar Borkar
,
Bill Dally
Papers
Towards a software approach to mitigate voltage emergencies
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pp. 123-128
by
Meeta Sharma Gupta
,
Krishna K. Rangan
,
Michael D. Smith
,
Gu-Yeon Wei
,
David Brooks
Papers
Improving disk reuse for reducing power consumption
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pp. 129-134
by
Mahmut Kandemir
,
Seung Woo Son
,
Mustafa Karakoy
Papers
PVS: passive voltage scaling for wireless sensor networks
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pp. 135-140
by
Youngjin Cho
,
Younghyun Kim
,
Naehyuck Chang
Papers
A programming environment with runtime energy characterization for energy-aware applications
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pp. 141-146
by
Changjiu Xian
,
Yung-Hsiang Lu
,
Zhiyuan Li
Papers
A process variation aware low power synthesis methodology for fixed-point FIR filters
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pp. 147-152
by
Nilanjan Banerjee
,
Jung Hwan Choi
,
Kaushik Roy
Papers
Voltage- and ABB-island optimization in high level synthesis
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pp. 153-158
by
Domenik Helms
,
Olaf Meyer
,
Marko Hoyer
,
Wolfgang Nebel
Papers
Power-optimal RTL arithmetic unit soft-macro selection strategy for leakage-sensitive technologies
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pp. 159-164
by
Simone Medardoni
,
Davide Bertozzi
,
Enrico Macii
Papers
Power signal processing: a new perspective for power analysis and optimization
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pp. 165-170
by
Quming Zhou
,
Lin Zhong
,
Kartik Mohanram
Papers
A 160 mV, fully differential, robust schmitt trigger based sub-threshold SRAM
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pp. 171-176
by
Jaydeep P. Kulkarni
,
Keejong Kim
,
Kaushik Roy
Papers
A low-power SRAM using bit-line charge-recycling technique
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pp. 177-182
by
Keejong Kim
,
Hamid Mahmoodi
,
Kaushik Roy
Papers
Minimizing power dissipation during write operation to register files
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pp. 183-188
by
Kimish Patel
,
Wonbok Lee
,
Massoud Pedram
Papers
An on-chip NBTI sensor for measuring PMOS threshold voltage degradation
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pp. 189-194
by
John Keane
,
Tae-Hyoung Kim
,
Chris H. Kim
Papers
Variable-latency adder (VL-adder): new arithmetic circuit design practice to overcome NBTI
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pp. 195-200
by
Yiran Chen
,
Hai Li
,
Jing Li
,
Cheng-Kok Koh
Papers
Throughput of multi-core processors under thermal constraints
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pp. 201-206
by
Ravishankar Rao
,
Sarma Vrudhula
,
Chaitali Chakrabarti
Papers
Dynamic voltage frequency scaling for multi-tasking systems using online learning
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pp. 207-212
by
Gaurav Dhiman
,
Tajana Simunic Rosing
Papers
Thermal-aware task scheduling at the system software level
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pp. 213-218
by
Jeonghwan Choi
,
Chen-Yong Cher
,
Hubertus Franke
,
Henrdrik Hamann
,
Alan Weger
,
Pradip Bose
Papers
Thermal response to DVFS: analysis with an Intel Pentium M
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pp. 219-224
by
Heather Hanson
,
Stephen W. Keckler
,
Soraya Ghiasi
,
Karthick Rajamani
,
Freeman Rawson
,
Juan Rubio
Papers
Approximation algorithms for power minimization of earliest deadline first and rate monotonic schedules
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pp. 225-230
by
Sushu Zhang
,
Karam S. Chatha
,
Goran Konjevod
Papers
The parallel computing landscape: a Berkeley view
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pp. 231-231
by
David Patterson
Papers
Low power soft-output signal detector design for wireless MIMO communication systems
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pp. 232-237
by
Sizhong Chen
,
Tong Zhang
Papers
A low power multimedia SoC with fully programmable 3D graphics and MPEG4/H.264/JPEG for mobile devices
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pp. 238-243
by
Jeong-Ho Woo
,
Ju-Ho Sohn
,
Hyejung Kim
,
Jongcheol Jeong
,
Euljoo Jeong
,
Suk Joong Lee
,
Hoi-Jun Yoo
Papers
An architecture for energy efficient sphere decoding
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pp. 244-249
by
Ravi Jenkal
,
Rhett Davis
Papers
On the selection of arithmetic unit structure in voltage overscaled soft digital signal processing
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pp. 250-255
by
Yang Liu
,
Tong Zhang
Papers
Low-power H.264/AVC baseline decoder for portable applications
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pp. 256-261
by
Ke Xu
,
Chiu Sing Choy
Papers
A 0.4-V UWB baseband processor
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pp. 262-267
by
Vivienne Sze
,
Anantha P. Chandrakasan
Papers
Resource area dilation to reduce power density in throughput servers
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pp. 268-273
by
Michael D. Powell
,
T. N. Vijaykumar
Papers
Locality-driven architectural cache sub-banking for leakage energy reduction
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pp. 274-279
by
Olga Golubeva
,
Mirko Loghi
,
Enrico Macii
,
Massimo Poncino
Papers
A multi-model power estimation engine for accuracy optimization
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pp. 280-285
by
Felipe Klein
,
G. Araujo
,
Rodolfo Azevedo
,
Roberto Leao
,
Luiz C. V. dos Santos
Papers
A fast-transient over-sampled delta-sigma adaptive DC-DC converter for power-efficient noise-sensitive devices
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pp. 286-291
by
Minkyu Song
,
Dongsheng Ma
Papers
High-efficiency synchronous dual-output switched-capacitor dc-dc converter with digital state machine control
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pp. 292-297
by
Han Shiming
,
Wu Xiaobo
,
Liu Yang
Papers
A micro power management system and maximum output power control for solar energy harvesting applications
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pp. 298-303
by
Hui Shao
,
Chi-Ying Tsui
,
Wing-Hung Ki
Papers
Advanced thermal sensing circuit and test techniques used in a high performance 65nm processor
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pp. 304-309
by
David E. Duarte
,
Greg Taylor
,
Keng L. Wong
,
Usman Mughal
,
George Geannopoulos
Papers
Single inductor, multiple input, multiple output (SIMIMO) power mixer-charger-supply system
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pp. 310-315
by
Min Chen
,
Gabriel A. Rincón-Mora
Papers
Vibration energy scavenging and management for ultra low power applications
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pp. 316-321
by
Lu Chao
,
Chi Ying Tsui
,
Wing Hung Ki
Papers
Energy management of DVS-DPM enabled embedded systems powered by fuel cell-battery hybrid source
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pp. 322-327
by
Jianli Zhuo
,
Chaitali Chakrabarti
,
Naehyuck Chang
Papers
Design of an efficient power delivery network in an soc to enable dynamic power management
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pp. 328-333
by
Behnam Amelifard
,
Massoud Pedram
Papers
Energy-efficient and performance-enhanced disks using flash-memory cache
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pp. 334-339
by
Jen-Wei Hsieh
,
Tei-Wei Kuo
,
Po-Liang Wu
,
Yu-Chung Huang
Papers
SAPP: scalable and adaptable peak power management in nocs
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pp. 340-345
by
Praveen S. Bhojwani
,
Jason D. Lee
,
Rabi N. Mahapatra
Papers
All watts considered
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pp. 346-346
by
Luiz Andre Barroso
Papers
A 65-nm pulsed latch with a single clocked transistor
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pp. 347-350
by
Martin Saint-Laurent
,
Baker Mohammad
,
Paul Bassett
Papers
A methodology for analysis and verification of power gated circuits with correlated results
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pp. 351-354
by
Aveek Sarkar
,
Shen Lin
,
Kai Wang
Papers
Vt balancing and device sizing towards high yield of sub-threshold static logic gates
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pp. 355-358
by
Yu Pu
,
Jose de jesus Pineda de Gyvez
,
Henk Corporaal
,
Yajun Ha
Papers
Power-efficient LDPC code decoder architecture
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pp. 359-362
by
Kazunori Shimizu
,
Nozomu Togawa
,
Takeshi Ikenaga
,
Satoshi Goto
Papers
A low-power CSCD asynchronous viterbi decoder for wireless applications
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pp. 363-366
by
Mohamed Kawokgy
,
C. André T. Salama
Papers
Reducing cache energy consumption by tag encoding in embedded processors
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pp. 367-370
by
Mingming Zhang
,
Xiaotao Chang
,
Ge Zhang
Papers
On reducing energy-consumption by late-inserting instructions into the issue queue
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pp. 371-374
by
Enric Morancho
,
José María Llabería
,
Àngel Olivé
Papers
Power-aware operand delivery
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pp. 375-378
by
Erika Gunadi
,
Mikko H. Lipasti
Papers
On the latency, energy and area of checkpointed, superscalar register alias tables
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pp. 379-382
by
Elham Safi
,
Patrick Akl
,
Andreas Moshovos
,
Andreas Veneris
,
Aggeliki Arapoyianni
Papers
Adaptive analog biasing: a robustness-enhanced low-power technique for analog baseband design
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pp. 383-386
by
Zhenhua Wang
Papers
Slope interconnect effort: gate-interconnect interdependentdelay model for CMOS logic gates
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pp. 387-390
by
Myeong-Eun Hwang
,
Seong-Ook Jung
,
Kaushik Roy
Papers
Electromigration and voltage drop aware power grid optimization for power gated ICs
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pp. 391-394
by
Aida Todri
,
Shih-Chieh Chang
,
Malgorzata Marek-Sadowska
Papers
Reducing display power in DVS-enabled handheld systems
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pp. 395-398
by
Jung-hi Min
,
Hojung Cha
Papers
Multicasting based topology generation and core mapping for a power efficient networks-on-chip
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pp. 399-402
by
Balasubramanian Sethuraman
,
Ranga Vemuri
Papers
Phase-aware adaptive hardware selection for power-efficient scientific computations
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pp. 403-406
by
Konrad Malkowski
,
Padma Raghavan
,
Mahmut Kandemir
,
Mary Jane Irwin
Papers
Signoff power methodology for contactless smartcards
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pp. 407-410
by
Julien Mercier
,
Christian Dufaza
,
Mathieu Lisart
Papers
An ilp based approach to reducing energy consumption in nocbased CMPS
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pp. 411-414
by
Ozcan Ozturk
,
Mahmut Kandemir
,
Seung W. Son
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