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Proceedings. 34th International Symposium on Multiple-Valued Logic

May 19 2004 to May 22 2004

University of Toronto, Toronto, Canada

ISSN: 0195-623X

ISBN: 0-7695-2130-4

Table of Contents

Introduction
Message from the Symposium Co-ChairsFreely available from IEEE.pp. xi
Introduction
Message from the Program ChairFreely available from IEEE.pp. xii
Introduction
Symposium CommitteeFreely available from IEEE.pp. xiii
Introduction
RefereesFreely available from IEEE.pp. xiv
Session 1 Keynote Address
Hard vs. Soft: The Central Question of Pre-Fabricated SiliconFull-text access may be available. Sign in or learn about subscription options.pp. 2-5
Session 2A Emerging Technologies
Multiple-Input Resonant-Tunneling Logic Gates for Flash A/D Converter ApplicationsFull-text access may be available. Sign in or learn about subscription options.pp. 8-13
Session 2A Emerging Technologies
A Novel Multiple-Valued Logic Design Using Ballistic Carbon Nanotube FETsFull-text access may be available. Sign in or learn about subscription options.pp. 14-19
Session 2A Emerging Technologies
Multiple-Valued Multiple-Rail Encoding Scheme for Low-Power Asynchronous CommunicationFull-text access may be available. Sign in or learn about subscription options.pp. 20-25
Session 2A Emerging Technologies
Ultra-Fine-Grain Field-Programmable VLSI Using Multiple-Valued Source-Coupled LogicFull-text access may be available. Sign in or learn about subscription options.pp. 26-30
Session 2B Logic
Resolution-Based Decision Procedures for the Positive Theory of Some Finitely Generated Varieties of AlgebrasFull-text access may be available. Sign in or learn about subscription options.pp. 32-37
Session 2B Logic
Uniform Description of Calculi for All t-Norm LogicsFull-text access may be available. Sign in or learn about subscription options.pp. 38-43
Session 2B Logic
Weakly Associative Functions on [0, 1] as Logical ConnectivesFull-text access may be available. Sign in or learn about subscription options.pp. 44-48
Session 2B Logic
Automata over MV-AlgebrasFull-text access may be available. Sign in or learn about subscription options.pp. 49-54
Session 3 Invited Address
Quantum Communication Complexity: A SurveyFull-text access may be available. Sign in or learn about subscription options.pp. 56
Session 4A Reversible Logic
Ternary Galois Field Expansions for Reversible Logic and Kronecker Decision Diagrams for Ternary GFSOP MinimizationFull-text access may be available. Sign in or learn about subscription options.pp. 58-67
Session 4A Reversible Logic
On Universality of General Reversible Multiple-Valued Logic GatesFull-text access may be available. Sign in or learn about subscription options.pp. 68-73
Session 4A Reversible Logic
A Synthesis Method for MVL Reversible LogicFull-text access may be available. Sign in or learn about subscription options.pp. 74-80
Session 4A Reversible Logic
Reversible Fast Permutation Transforms for Quantum Circuit SynthesisFull-text access may be available. Sign in or learn about subscription options.pp. 81-86
Session 4A Reversible Logic
Quantum Circuit Synthesis Using Classes of GF(3) Reversible Fast Spectral TransformsFull-text access may be available. Sign in or learn about subscription options.pp. 87-93
Session 4B Clones
On Partial Clones containing Maximal ClonesFull-text access may be available. Sign in or learn about subscription options.pp. 96-101
Session 4B Clones
Monoids whose Centralizer is the Least CloneFull-text access may be available. Sign in or learn about subscription options.pp. 102-108
Session 4B Clones
Algebraic Properties of Totally Irreducible Elements of Clone LatticesFull-text access may be available. Sign in or learn about subscription options.pp. 109-114
Session 4B Clones
Minimal Partial Hyperclones on a Two-Element SetFull-text access may be available. Sign in or learn about subscription options.pp. 115-119
Session 4B Clones
Some Properties of Local Partial Clones on an Infinite SetFull-text access may be available. Sign in or learn about subscription options.pp. 120-125
Session 5A Circuits I
Signed Digit CMOS (SD-CMOS) Logic Circuits with Static OperationFull-text access may be available. Sign in or learn about subscription options.pp. 128-134
Session 5A Circuits I
A Systolic Parallel Multiplier over GF(3m) Using Neuron-MOS DLCFull-text access may be available. Sign in or learn about subscription options.pp. 135-138
Sesion 5B Fuzzy Logic and Learning
Optimizing the Defuzzifier Timing for the Fuzzy Control of a ServodriveFull-text access may be available. Sign in or learn about subscription options.pp. 142-147
Sesion 5B Fuzzy Logic and Learning
A Metasemantics to Refine Fuzzy If-Then RulesFull-text access may be available. Sign in or learn about subscription options.pp. 148-153
Sesion 5B Fuzzy Logic and Learning
Evolutionary Strategy for Learning Multiple-Valued Logic FunctionsFull-text access may be available. Sign in or learn about subscription options.pp. 154-160
Session 6A Reed Muller Expansions
Fast Optimization of Fixed-Polarity Reed-Muller Expansions over GF(5)Full-text access may be available. Sign in or learn about subscription options.pp. 162-167
Session 6A Reed Muller Expansions
On the Optimisation of Reed-Muller ExpressionsFull-text access may be available. Sign in or learn about subscription options.pp. 168-176
Session 6A Reed Muller Expansions
Spectra Generation for Fixed-Polarity Reed-Muller Transform over GF(5)Full-text access may be available. Sign in or learn about subscription options.pp. 177-183
Session 6A Reed Muller Expansions
Derivatives for Multiple-Valued Functions Induced by Galois Field and Reed-Muller-Fourier ExpressionsFull-text access may be available. Sign in or learn about subscription options.pp. 184-189
Session 6B Circuits II
Intra-Chip Address-Presetting Data-Transfer Scheme Using Four-Valued EncodingFull-text access may be available. Sign in or learn about subscription options.pp. 192-197
Session 6B Circuits II
Design of Quaternary Logic Gate Using Double Pass-Transistor Logic with Neuron MOS Down Literal CircuitFull-text access may be available. Sign in or learn about subscription options.pp. 198-203
Session 6B Circuits II
A Self-Restored Current-Mode CMOS Multiple-Valued Logic Design Technique and its ApplicationsFull-text access may be available. Sign in or learn about subscription options.pp. 204-209
Session 6B Circuits II
A Novel D-Latch in Multiple-Valued Semi-Floating-Gate Recharged LogicFull-text access may be available. Sign in or learn about subscription options.pp. 210-213
Session 8A MDDs
On the Minimization of Average Path Lengths for Heterogeneous MDDsFull-text access may be available. Sign in or learn about subscription options.pp. 216-222
Session 8A MDDs
Reduction of Sizes of Multi-Valued Decision Diagrams by Copy PropertiesFull-text access may be available. Sign in or learn about subscription options.pp. 223-228
Session 8A MDDs
Edge-Valued Decision Diagrams for Multiple-Valued FunctionsFull-text access may be available. Sign in or learn about subscription options.pp. 229-234
Session 8A MDDs
Algorithms for Taylor Expansion DiagramsFull-text access may be available. Sign in or learn about subscription options.pp. 235-240
Session 8B Mathematical Aspects
Polynomial Functions on a Central RelationFull-text access may be available. Sign in or learn about subscription options.pp. 242-244
Session 8B Mathematical Aspects
A Graph-Theoretical Approach to Boolean Interpolation of Non-Boolean FunctionsFull-text access may be available. Sign in or learn about subscription options.pp. 245-250
Session 8B Mathematical Aspects
The Interface between P and NP in Signed CNF FormulasFull-text access may be available. Sign in or learn about subscription options.pp. 251-256
Session 8B Mathematical Aspects
Characterization Theorem of Lattice Implication AlgebrasFull-text access may be available. Sign in or learn about subscription options.pp. 257-260
Session 9A Single Electron Logic
Three Dimensional Multiple Valued Circuits Design Based on Single-Electron LogicFull-text access may be available. Sign in or learn about subscription options.pp. 275-280
Session 9B Probability & Uncertainty
Non-Deterministic MatricesFull-text access may be available. Sign in or learn about subscription options.pp. 282-287
Session 9B Probability & Uncertainty
Controlling Uncertainty in Discretization of Continuous DataFull-text access may be available. Sign in or learn about subscription options.pp. 288-293
Session 9B Probability & Uncertainty
Many Valued Probability TheoryFull-text access may be available. Sign in or learn about subscription options.pp. 294-299
Session 10A Digital Design
A Method to Evaluate Logic Functions in the Presence of Unknown Inputs Using LUT CascadesFull-text access may be available. Sign in or learn about subscription options.pp. 302-308
Session 10A Digital Design
A Polynomial Time Algorithm for Non-Disjoint Decomposition of Multiple-Valued FunctionsFull-text access may be available. Sign in or learn about subscription options.pp. 309-314
Session 10A Digital Design
Iterative-Based Minimization of Unary 4-Valued Functions for Current-Mode CMOS RealizationFull-text access may be available. Sign in or learn about subscription options.pp. 315-320
Session 10A Digital Design
On the Minimization of Multiple-Valued Input Binary-Valued Output FunctionsFull-text access may be available. Sign in or learn about subscription options.pp. 321-326
Session 10B Circuits III
Multiple-Valued Source-Coupled Logic VLSI Based on Adaptive Threshold Control and Its ApplicationsFull-text access may be available. Sign in or learn about subscription options.pp. 328-333
Session 10B Circuits III
Design and Verification of Parallel Multipliers Using Arithmetic Description Language: ARITHFull-text access may be available. Sign in or learn about subscription options.pp. 334-339
Session 10B Circuits III
A Study of Multiple-Valued Magnetoresistive RAM (MRAM) Using Binary MTJ DevicesFull-text access may be available. Sign in or learn about subscription options.pp. 340-345
Session 10B Circuits III
Basic Multiple-Valued Functions Using Recharge CMOS LogicFull-text access may be available. Sign in or learn about subscription options.pp. 346-351
Author Index
Author IndexFreely available from IEEE.pp. 352-353
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