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2008 9th International Symposium on Quality Electronic Design (ISQED '08)

March 17 2008 to March 19 2008

San Jose, CA

Table of Contents

Organizing Committee / Best PaperFreely available from IEEE.
Conference at a glanceFreely available from IEEE.
Tutorial 1: The Promise of High-k/Metal Gates-From Electronic Transport Phenomena to Emerging Device/Circuit ApplicationsFull-text access may be available. Sign in or learn about subscription options.pp. 3-3
by K. Maitra
Tutorial 2: Low Voltage Circuit Design Techniques for Sub-32nm TechnologiesFull-text access may be available. Sign in or learn about subscription options.pp. 4-4
by Chris Kim
Tutorial 3: Process Technology Development and New Design Opportunities in 3D Integration TechnologyFull-text access may be available. Sign in or learn about subscription options.pp. 5-5
by Robert E. Jones
Tutorial 4: Robust System Design in Scaled CMOSFull-text access may be available. Sign in or learn about subscription options.pp. 6-6
by Subhasis Mitra
Tutorial 5: Caches in the Many-Core Era: What Purpose Might eDRAM Serve?Full-text access may be available. Sign in or learn about subscription options.pp. 7-7
by Hillary Hunter
Tutorial 6: Enhancing Yield through Design for Manufacturability (DFM)Full-text access may be available. Sign in or learn about subscription options.pp. 8-9
by Praveen Elakkumanan
Papers
Page iFreely available from IEEE.pp. i
Papers
Title Page iiiFreely available from IEEE.pp. iii
Papers
Copyright PageFreely available from IEEE.pp. iv
Papers
Table of ContentsFreely available from IEEE.pp. v-xviii
Papers
Welcome NotesFreely available from IEEE.pp. xix-xx
Papers
Organizing Committee/Best PaperFreely available from IEEE.pp. xxi
Speed-Up of ASICs Derived from FPGAs by Transistor Network Synthesis Including ReorderingFull-text access may be available. Sign in or learn about subscription options.pp. 47-52
by Tiago Muller Gil Cardoso, Felipe de Souza Marques, Renato Perez Ribas, Andre Inacio Reis, Leomar Soares da Rosa Jr.
Papers
Technical Subcommittee ListsFreely available from IEEE.pp. xxii-xxv
Papers
Steering/Advisory CommitteeFreely available from IEEE.pp. xxvi
Papers
Conference at a GlanceFreely available from IEEE.pp. xxvii-xxviii
Papers
Tutorial 1: The Promise of High-?/Metal Gates-From Electronic Transport Phenomena to Emerging Device/Circuit ApplicationsFull-text access may be available. Sign in or learn about subscription options.pp. 3
by K. Maitra
Papers
Plenary Speech 1P1: Shrinking time-to-market through global value chain integrationFull-text access may be available. Sign in or learn about subscription options.pp. 15
by Drew Gude
Quality of a Bit (QoB): A New Concept in Dependable SRAMFull-text access may be available. Sign in or learn about subscription options.pp. 98-102
by Hidehiro Fujiwara, Shunsuke Okumura, Yusuke Iguchi, Hiroki Noguchi, Yasuhiro Morita, Hiroshi Kawaguchi, Masahiko Yoshimoto
Papers
Plenary Speech 1P2: Bounding the Endless Verification LoopFull-text access may be available. Sign in or learn about subscription options.pp. 16-17
by Robert Hum
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A Radiation Hardened Nano-Power 8Mb SRAM in 130nm CMOSFull-text access may be available. Sign in or learn about subscription options.pp. 23-29
by Mark Lysinger, Francois Jacquet, Mehdi Zamanian, David McClure, Philippe Roche, Naren Sahoo, John Russell
Papers
Error-Tolerant SRAM Design for Ultra-Low Power Standby OperationFull-text access may be available. Sign in or learn about subscription options.pp. 30-34
by Huifang Qin, Animesh Kumar, Kannan Ramchandran, Jan Rabaey, Prakash Ishwar
Papers
Error Protected Data Bus Inversion Using Standard DRAM ComponentsFull-text access may be available. Sign in or learn about subscription options.pp. 35-42
by Maurzio Skerlj, Paolo Ienne
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Process Variation Aware Bus-Coding Scheme for Delay Minimization in VLSI InterconnectsFull-text access may be available. Sign in or learn about subscription options.pp. 43-46
by Chittarsu Raghunandan, K.S. Sainarayanan, M.B. Srinivas
Papers
Fast and Accurate Waveform Analysis with Current Source ModelsFull-text access may be available. Sign in or learn about subscription options.pp. 53-56
by Vineeth Veetil, Dennis Sylvester, David Blaauw
Dependence of Minimum Operating Voltage (VDDmin) on Block Size of 90-nm CMOS Ring Oscillators and its Implications in Low Power DFMFull-text access may be available. Sign in or learn about subscription options.
by Taro Niiyama, Piao Zhe, Koichi Ishida, Masami Murakata, Makoto Takamiya, Takayasu Sakurai
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An Efficient Method for Fast Delay and SI Calculation Using Current Source ModelsFull-text access may be available. Sign in or learn about subscription options.pp. 57-61
by Xin Wang, Ali Kasnavi, Harold Levy
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Adaptive Stochastic Collocation Method (ASCM) for Parameterized Statistical Timing Analysis with Quadratic Delay ModelFull-text access may be available. Sign in or learn about subscription options.pp. 62-67
by Yi Wang, Xuan Zeng, Jun Tao, Hengliang Zhu, Xu Luo, Changhao Yan, Wei Cai
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Combinational Logic Circuit Protection Using Customized Error Detecting and Correcting CodesFull-text access may be available. Sign in or learn about subscription options.pp. 68-73
by Avijit Dutta, Abhijit Jas
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Output Remapping Technique for Soft-Error Rate Reduction in Critical PathsFull-text access may be available. Sign in or learn about subscription options.pp. 74-77
by Qian Ding, Yu Wang, Hui Wang, Rong Luo, Huazhong Yang
Papers
IR Drop Reduction via a Flip-Flop Resynthesis TechniqueFull-text access may be available. Sign in or learn about subscription options.pp. 78-83
by Jiun-Kuan Wu, Tsung-Yi Wu, Liang-Ying Lu, Kuang-Yao Chen
Papers
Noise Interaction Between Power Distribution Grids and SubstrateFull-text access may be available. Sign in or learn about subscription options.pp. 84-89
by Daniel A. Andersson, Simon Kristiansson, Lars J. Svensson, Per Larsson-Edefors, Kjell O. Jeppson
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Luncheon Keynote SpeechFull-text access may be available. Sign in or learn about subscription options.pp. 90-91
by Antun Domic
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Fundamental Data Retention Limits in SRAM Standby Experimental ResultsFull-text access may be available. Sign in or learn about subscription options.pp. 92-97
by Animesh Kumar, Huifang Qin, Prakash Ishwar, Jan Rabaey, Kannan Ramchandran
Papers
Cache Design for Low Power and High YieldFull-text access may be available. Sign in or learn about subscription options.pp. 103-107
by Baker Mohammad, Martin Saint-Laurent, Paul Bassett, Jacob Abraham
Papers
Projection-Based Piecewise-Linear Response Surface Modeling for Strongly Nonlinear VLSI Performance VariationsFull-text access may be available. Sign in or learn about subscription options.pp. 108-113
by Xin Li, Yu Cao
Papers
High Output Resistance and Wide Swing Voltage Charge Pump CircuitFull-text access may be available. Sign in or learn about subscription options.pp. 114-117
by Tian Xia, Stephen Wyatt
Papers
Interconnect Signaling and Layout Optimization to Manage Thermal Effects Due to Self Heating in On-Chip Signal BusesFull-text access may be available. Sign in or learn about subscription options.pp. 118-122
by Krishnan Sundaresan, Nihar R. Mahapatra
Papers
A Low-Power Double-Edge-Triggered Address Pointer Circuit for FIFO Memory DesignFull-text access may be available. Sign in or learn about subscription options.pp. 123-126
by Saravanan Ramamoorthy, Haibo Wang, Sarma Vrudhula
Papers
Minimizing Offset for Latching Voltage-Mode Sense Amplifiers for Sub-Threshold OperationFull-text access may be available. Sign in or learn about subscription options.pp. 127-132
by Joseph F. Ryan, Benton H. Calhoun
Papers
Dependence of Minimum Operating Voltage (VDDmin) on Block Size of 90-nm CMOS Ring Oscillators and its Implications in Low Power DFMFull-text access may be available. Sign in or learn about subscription options.pp. 133-136
by Taro Niiyama, Piao Zhe, Koichi Ishida, Masami Murakata, Makoto Takamiya, Takayasu Sakurai
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Accurate Temperature Estimation for Efficient Thermal ManagementFull-text access may be available. Sign in or learn about subscription options.pp. 137-142
by Shervin Sharifi, ChunChen Liu, Tajana Simunic Rosing
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Process Variation Aware Timing Optimization through Transistor Sizing in Dynamic CMOS LogicFull-text access may be available. Sign in or learn about subscription options.pp. 143-147
by Kumar Yelamarthi, Chien-In Henry Chen
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Compact Variation-Aware Standard Cell Models for Timing Analysis - Complexity and Accuracy AnalysisFull-text access may be available. Sign in or learn about subscription options.pp. 148-151
by Seyed-Abdollah Aftabjahani, Linda S. Milor
Papers
A Statistical Characterization of CMOS Process Fluctuations in Subthreshold Current MirrorsFull-text access may be available. Sign in or learn about subscription options.pp. 152-155
by Lei Zhang, Zhiping Yu, Xiangqing He
Papers
Robust Estimation of Timing Yield with Partial Statistical Information on Process VariationsFull-text access may be available. Sign in or learn about subscription options.pp. 156-161
by Lin Xie, Azadeh Davoodi
A Dual Oxide CMOS Universal Voltage Converter for Power Management in Multi-VDD SoCsFull-text access may be available. Sign in or learn about subscription options.
by Dhruva Ghai, Saraju P. Mohanty, Elias Kougianos
Papers
Variation Aware Spline Center and Range Modeling for Analog Circuit PerformanceFull-text access may be available. Sign in or learn about subscription options.pp. 162-167
by Shubhankar Basu, Balaji Kommineni, Ranga Vemuri
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High-Quality Circuit Synthesis for Modern TechnologiesFull-text access may be available. Sign in or learn about subscription options.pp. 168-173
by Lech Jozwiak, Artur Chojnacki, Aleksander Slusarczyk
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ILP Based Gate Leakage Optimization Using DKCMOS Library during RTL SynthesisFull-text access may be available. Sign in or learn about subscription options.pp. 174-177
by Saraju P. Mohanty
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Improving the Efficiency of Power Management Techniques by Using Bayesian ClassificationFull-text access may be available. Sign in or learn about subscription options.pp. 178-183
by Hwisung Jung, Massoud Pedram
Papers
An On-Demand Test Triggering Mechanism for NoC-Based Safety-Critical SystemsFull-text access may be available. Sign in or learn about subscription options.pp. 184-189
by Jason D. Lee, Nikhil Gupta, Praveen S. Bhojwani, Rabi N. Mahapatra
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Constant Rate Dataflow Model with Intermediate Ports for Efficient Code Synthesis with Top-Down Design and Dynamic BehaviorFull-text access may be available. Sign in or learn about subscription options.pp. 190-193
by Hyunok Oh
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Thermal-Aware IR Drop Analysis in Large Power GridFull-text access may be available. Sign in or learn about subscription options.pp. 194-199
by Yu Zhong, Martin D.F. Wong
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A Methodology for Characterization of Large Macro Cells and IP Blocks Considering Process VariationsFull-text access may be available. Sign in or learn about subscription options.pp. 200-206
by Amit Goel, Sarma Vrudhula, Feroze Taraporevala, Praveen Ghanta
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Investigation of Process Impact on Soft Error Susceptibility of Nanometric SRAMs Using a Compact Critical Charge ModelFull-text access may be available. Sign in or learn about subscription options.pp. 207-212
by Shah M. Jahinuzzaman, Mohammad Sharifkhani, Manoj Sachdev
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Characterization of Standard Cells for Intra-Cell Mismatch VariationsFull-text access may be available. Sign in or learn about subscription options.pp. 213-219
by Savithri Sundareswaran, Jacob A. Abraham, Alexandre Ardelea, Rajendran Panda
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Full-Chip Leakage Verification for Manufacturing Considering Process VariationsFull-text access may be available. Sign in or learn about subscription options.pp. 220-223
by Tao Li, Zhiping Yu
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Processor Verification with hwBugHuntFull-text access may be available. Sign in or learn about subscription options.pp. 224-229
by Sangeetha Sudhakrishnan, Liying Su, Jose Renau
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Enhancing the Testability of RTL Designs Using Efficiently Synthesized AssertionsFull-text access may be available. Sign in or learn about subscription options.pp. 230-235
by Mohammad Reza Kakoee, Mohammad Riazati, Siamak Mohammadi
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Efficient Selection of Observation Points for Functional TestsFull-text access may be available. Sign in or learn about subscription options.pp. 236-241
by Jian Kang, Sharad C. Seth, Yi-Shing Chang, Vijay Gangaram
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A Novel Test Generation Methodology for Adaptive DiagnosisFull-text access may be available. Sign in or learn about subscription options.pp. 242-245
by Rajsekhar Adapa, Edward Flanigan, Spyros Tragoudas
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Timing-Aware Multiple-Delay-Fault DiagnosisFull-text access may be available. Sign in or learn about subscription options.pp. 246-253
by Vishal J. Mehta, Malgorzata Marek-Sadowska, Kun-Han Tsai, Janusz Rajski
Papers
A Dual Oxide CMOS Universal Voltage Converter for Power Management in Multi-VDD SoCsFull-text access may be available. Sign in or learn about subscription options.pp. 257-260
by Dhruva Ghai, Saraju P. Mohanty, Elias Kougianos
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Dominant Substrate Noise Coupling Mechanism for Multiple Switching GatesFull-text access may be available. Sign in or learn about subscription options.pp. 261-266
by Emre Salman, Eby G. Friedman, Radu M. Secareanu, Olin L. Hartin
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A Statistic-Based Approach to Testability AnalysisFull-text access may be available. Sign in or learn about subscription options.pp. 267-270
by Chuang-Chi Chiou, Chun-Yao Wang, Yung-Chih Chen
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Generic Carrier-Based Core Model for Four-Terminal Double-Gate MOSFET Valid for Symmetric, Asymmetric, SOI, and Independent Gate Operation ModesFull-text access may be available. Sign in or learn about subscription options.pp. 271-276
by Feng Liu, Jin He, Yue Fu, Jinhua Hu, Wei Bian, Yan Song, Xing Zhang, Mansun Chan
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On the Feasibility of Obtaining a Globally Optimal Floorplanning for an L-shaped Layout ProblemFull-text access may be available. Sign in or learn about subscription options.pp. 277-282
by Tsu-Shuan Chang, Manish Kumar, Teng S. Moh, Chung-Li Tseng
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Architecting for Physical Verification Performance and ScalingFull-text access may be available. Sign in or learn about subscription options.pp. 283-288
by John Ferguson, Robert Todd
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Efficient Thermal Aware Placement Approach Integrated with 3D DCT Placement AlgorithmFull-text access may be available. Sign in or learn about subscription options.pp. 289-292
by Haixia Yan, Qiang Zhou, Xianlong Hong
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CMOS Based Low Cost Temperature SensorFull-text access may be available. Sign in or learn about subscription options.pp. 293-296
by Neehar Jandhyala, Lili He, Morris Jones
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An SSO Based Methodology for EM Emission Estimation from SoCsFull-text access may be available. Sign in or learn about subscription options.pp. 297-300
by S. Jairam, S.M. Stalin, Jean-Yves Oberle, H. Udayakumar
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Fast Timing Update under the Effect of IR DropFull-text access may be available. Sign in or learn about subscription options.pp. 301-304
by Muzhou Shao
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Statistical Data Stability and Leakage Evaluation of FinFET SRAM Cells with Dynamic Threshold Voltage Tuning under Process Parameter FluctuationsFull-text access may be available. Sign in or learn about subscription options.pp. 305-310
by Zhiyu Liu, Sherif A. Tawfik, Volkan Kursun
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Characterization of New Static Independent-Gate-Biased FinFET Latches and Flip-Flops under Process VariationsFull-text access may be available. Sign in or learn about subscription options.pp. 311-316
by Sherif A. Tawfik, Volkan Kursun
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A Low Energy Two-Step Successive Approximation Algorithm for ADC DesignFull-text access may be available. Sign in or learn about subscription options.pp. 317-320
by Ricky Yiu-kee Choi, Chi-ying Tsui
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Automated Specific Instruction Customization Methodology for Multimedia Processor AccelerationFull-text access may be available. Sign in or learn about subscription options.pp. 321-324
by Kang Zhao, Jinian Bian, Sheqin Dong, Yang Song, Satoshi Goto
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Process Variability Analysis in DSM Through Statistical Simulations and its Implications to Design MethodologiesFull-text access may be available. Sign in or learn about subscription options.pp. 325-329
by Srinivasa R STG, Jandhyala Srivatsava, Narahari Tondamuthuru R
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Parasitic Aware Process Variation Tolerant Voltage Controlled Oscillator (VCO) DesignFull-text access may be available. Sign in or learn about subscription options.pp. 330-333
by Dhruva Ghai, Saraju P. Mohanty, Elias Kougianos
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Evaluation of the PTSI Crosstalk Noise Analysis Tool and Development of an Automated Spice Correlation Suite to Enable Accuracy ValidationFull-text access may be available. Sign in or learn about subscription options.pp. 334-337
by C.R. Venugopal, Prasanth Soraiyur, Jagannath Rao
A Fully-Integrated 2.4 GHz  Mismatch-Controllable RF Front-end Test Platform in 0.18µm CMOSFull-text access may be available. Sign in or learn about subscription options.
by Zahra Sadat Ebadi, Resve Saleh
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Hotspot Based Yield Prediction with Consideration of CorrelationsFull-text access may be available. Sign in or learn about subscription options.pp. 338-343
by Qing Su, Charles Chiang, Jamil Kawa
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A Randomized Greedy Algorithm for the Pattern Fill Problem for DFM ApplicationsFull-text access may be available. Sign in or learn about subscription options.pp. 344-347
by Maharaj Mukherjee, Kanad Chakraborty
A Robust and Efficient Pre-Silicon Validation Environment for Mixed-Signal Circuits on Intel's Test ChipsFull-text access may be available. Sign in or learn about subscription options.
by Nathaniel August
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A Passive 915 MHz UHF RFID TagFull-text access may be available. Sign in or learn about subscription options.pp. 348-351
by Jos? C.S. Palma, C?sar Marcon, Fabiano Hessel, Eduardo Bezerra, Guilherme Rohde, Luciano Azevedo, Carlos Reif, Carolina Metzler
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Crosstalk Noise Variation Assessment and Analysis for the Worst Process CornerFull-text access may be available. Sign in or learn about subscription options.pp. 352-356
by Jae-Seok Yang, Andrew R. Neureuther
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DFM Based Detailed Routing Algorithm for ECP and CMPFull-text access may be available. Sign in or learn about subscription options.pp. 357-360
by Yin Shen, Yici Cai, Qiang Zhou, Xianlong Hong
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Instruction Scheduling for Variation-Originated Variable LatenciesFull-text access may be available. Sign in or learn about subscription options.pp. 361-364
by Toshinori Sato, Shingo Watanabe
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Hotspot Prevention Using CMP Model in Design Implementation FlowFull-text access may be available. Sign in or learn about subscription options.pp. 365-368
by Norma Rodriguez, Li Song, Shishir Shroff, Kuang Han Chen, Taber Smith, Wilbur Luo
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The Statistical Failure Analysis for the Design of Robust SRAM in Nano-Scale EraFull-text access may be available. Sign in or learn about subscription options.pp. 369-372
by Young-Gu Kim, Soo-Hwan Kim, Hoon Lim, Sanghoon Lee, Keun-Ho Lee, Young-Kwan Park, Moon-Hyun Yoo
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Computation of Waveform Sensitivity Using Geometric Transforms for SSTAFull-text access may be available. Sign in or learn about subscription options.pp. 373-378
by Ratnakar Goyal, Harindranath Parameswaran, Sachin Shrivastava
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On Efficient and Robust Constraint Generation for Practical Layout LegalizationFull-text access may be available. Sign in or learn about subscription options.pp. 379-384
by Sambuddha Bhattacharya, Shabbir H. Batterywala, Subramanian Rajagopalan, Hi-Keung Tony Ma, Narendra V. Shenoy
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Feedback-Switch Logic (FSL): A High-Speed Low-Power Differential Dynamic-Like Static CMOS Circuit FamilyFull-text access may be available. Sign in or learn about subscription options.pp. 385-390
by Charbel J. Akl, Magdy A. Bayoumi
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Analysis of System-Level Reliability Factors and Implications on Real-Time Monitoring Methods for Oxide Breakdown Device FailuresFull-text access may be available. Sign in or learn about subscription options.pp. 391-395
by Eric Karl, Dennis Sylvester, David Blaauw
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Characterizing the Impact of Substrate Noise on High-Speed Flash ADCsFull-text access may be available. Sign in or learn about subscription options.pp. 396-400
by Parastoo Nikaeen, Boris Murmann, Robert W. Dutton
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Analytical Noise-Rejection Model Based on Short Channel MOSFETFull-text access may be available. Sign in or learn about subscription options.pp. 401-406
by Vinay Jain, Payman Zarkesh-Ha
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A High-Performance Bus Architecture for Strongly Coupled InterconnectsFull-text access may be available. Sign in or learn about subscription options.pp. 407-410
by Michael N. Skoufis, Kedar Karmarkar, Themistoklis Haniotakis, Spyros Tragoudas
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A Fully-Integrated 2.4 GHz??Mismatch-Controllable RF Front-end Test Platform in 0.18?m CMOSFull-text access may be available. Sign in or learn about subscription options.pp. 411-416
by Zahra Sadat Ebadi, Resve Saleh
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