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IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures (ISVLSI'06)

March 2 2006 to March 3 2006

Karlsruhe

Table of Contents

IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures - Title PageFreely available from IEEE.pp. i-iii
IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and ArchitecturesFreely available from IEEE.
IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures - Table of contentsFreely available from IEEE.pp. v-xii
Message from the General and Program ChairsFreely available from IEEE.pp. xiii-xiii
Introduction
Symposium committeesFreely available from IEEE.pp. xiv-xiv
Keynotes
Advanced Channel Decoding Algorithms and Their Implementation for Future Communication SystemsFreely available from IEEE.pp. 3-3
by N. Wehn
Keynotes
Multiprocessor Systems-on-ChipsFreely available from IEEE.pp. 4-4
by W. Wolf
Intellectual Property and Design
Floorplanning based on particle swarm optimizationFull-text access may be available. Sign in or learn about subscription options.pp. 5 pp.-5 pp.
by Tsung-Ying Sun, Sheng-Ta Hsieh, Hsiang-Min Wang, Cheng-Wei Lin
Autonomous realization of Boeing/JPL sensor electronics based on reconfigurable system-on-chip technologyFull-text access may be available. Sign in or learn about subscription options.pp. 6 pp.
by E.F. Stefatos, T. Arslan, D. Keymeulen, I. Ferguson
Intellectual Property and Design
Enhanced dual strategy based VLSI architecture for computing pseudo inverse of channel matrix in a MIMO wireless systemFull-text access may be available. Sign in or learn about subscription options.pp. 6 pp.
by Z. Khan, T. Arslan, J.S. Thompson, A.T. Erdogan
Intellectual Property and Design
Adaptive porting of analog IPs with reusable conservative propertiesFull-text access may be available. Sign in or learn about subscription options.pp. 6 pp.
by T. Nojima, S. Nakatake, T. Fujimura, K. Okazaki, Y. Kajitani, N. Ono
Intellectual Property and Design
VLSI design exchange with intellectual property protection in FPGA environment using both secret and public-key cryptographyFull-text access may be available. Sign in or learn about subscription options.pp. 6 pp.
by W. Adi, R. Ernst, B. Soudan, A. Hanoun
Physical Design
Metal fix and power network repair for SOCFull-text access may be available. Sign in or learn about subscription options.pp. 5 pp.
by Q.K. Zhu, P. Kolze
Physical Design
Multi-SP: a representation with united rectangles for analog placement and routingFull-text access may be available. Sign in or learn about subscription options.pp. 6 pp.
by Ning Fu, S. Nakatake, M. Mineshima
Physical Design
Formulating the empirical strategies in module generation of analog MOS layoutFull-text access may be available. Sign in or learn about subscription options.pp. 6 pp.
by Tan Yan, T. Nojima, S. Nakatake
Physical Design
An integer linear programming based approach to simultaneous memory space partitioning and data allocation for chip multiprocessorsFull-text access may be available. Sign in or learn about subscription options.pp. 6 pp.-6 pp.
by O. Ozturk, G. Chen, M. Kandemir, M. Karakoy
High Performance Circuits
High speed low swing dynamic circuits with multiple supply and threshold voltagesFull-text access may be available. Sign in or learn about subscription options.pp. 6 pp.
by Zhiyu Liu, V. Kursun
High Performance Circuits
High performance service-time-stamp computation for WFQ IP packet schedulingFull-text access may be available. Sign in or learn about subscription options.pp. 6 pp.
by C. McKillen, S. Sezer, Xin Xang
High Performance Circuits
Synthesis of pipelined SRSL circuitsFull-text access may be available. Sign in or learn about subscription options.pp. 6 pp.-6 pp.
by R. Oreifej, A. Alsharqawi, A. Ejnioui
High Performance Circuits
An efficient hardware implementation of a self-adaptable equalizer for WCDMA downlink UMTS standardFull-text access may be available. Sign in or learn about subscription options.pp. 5 pp.-5 pp.
by R.B. Prudencio, L.S. Indrusiak, M. Glesner
Reconfigurable Systems Integration
Defect-aware design paradigm for reconfigurable architecturesFull-text access may be available. Sign in or learn about subscription options.pp. 6 pp.
by R. Jain, A. Mukherjee, K. Paul
Reconfigurable Systems Integration
New 2-dimensional partial dynamic reconfiguration techniques for real-time adaptive microelectronic circuitsFull-text access may be available. Sign in or learn about subscription options.pp. 6 pp.
by M. Hiibner, C. Schuck, M. Kiihnle, J. Becker
Reconfigurable Systems Integration
A "soft++" eFPGA physical design approach with case studies in 180nm and 90nmFull-text access may be available. Sign in or learn about subscription options.pp. 6 pp.
by V. Aken'Ova, R. Saleh
Reconfigurable Systems Integration
QUKU: a two-level reconfigurable architectureFull-text access may be available. Sign in or learn about subscription options.pp. 6 pp.
by S. Shukla, N.W. Bergmann, J. Becker
A low power pipelined maximum likelihood detector for 4/spl times/4 QPSK MIMO wireless communication systemsFull-text access may be available. Sign in or learn about subscription options.pp. 5 pp.-5 pp.
by J.H. Han, A.T. Erdogan, T. Arslan
Mixed-Signal Design and Analysis
Space-saving layout for passive componentsFull-text access may be available. Sign in or learn about subscription options.pp. 5 pp.
by P.H. Karjalainen, P. Heino
Mixed-Signal Design and Analysis
A novel low power multilevel current mode interconnect systemFull-text access may be available. Sign in or learn about subscription options.pp. 6 pp.
by S. Joshi, D. Sharma
Globally asynchronous locally synchronous wrapper circuit based on clock gatingFull-text access may be available. Sign in or learn about subscription options.pp. 6 pp.
by E. Amini, M. Najibi, H. Pedram
Mixed-Signal Design and Analysis
The design of analog front-end circuitry for 1x HD-DVD PRML read channelFull-text access may be available. Sign in or learn about subscription options.pp. 5 pp.
by Sheng-Jang Lin, I-Shun Chen, Bo-Wei Chen, Feng-Hsiang Lo
Mixed-Signal Design and Analysis
Adaptive signal processing in mixed-signal VLSI with anti-Hebbian learningFull-text access may be available. Sign in or learn about subscription options.pp. 6 pp.
by M. Figueroa, E. Matamala, G. Carvajal, S. Bridges
Test and Verification
Verification of scheduling in high-level synthesisFull-text access may be available. Sign in or learn about subscription options.pp. 6 pp.
by C. Karfa, C. Mandal, D. Sarkar, S.R. Pentakota, C. Reade
Test and Verification
An efficient wrapper scan chain configuration method for network-on-chip testingFull-text access may be available. Sign in or learn about subscription options.pp. 6 pp.
by Ming Li, Wen-Ben Jone, Qing-An Zeng
Test and Verification
An efficient data-independent technique for compressing test vectors in systems-on-a-chipFull-text access may be available. Sign in or learn about subscription options.pp. 6 pp.
by Xiaoyu Ruan, Rajendra Katti
Test and Verification
Methods for run-time failure recognition and recovery in dynamic and partial reconfigurable systems based on Xilinx Virtex-II Pro FPGAsFull-text access may be available. Sign in or learn about subscription options.pp. 6 pp.
by K. Paulsson, M. Hubner, M. Jung, J. Becker
Low Power System Design
Design and analysis of a low power VLIW DSP coreFull-text access may be available. Sign in or learn about subscription options.pp. 6 pp.
by Chan-Hao Chang, D. Marculescu
Low Power System Design
High-performance noise-robust asynchronous circuitsFull-text access may be available. Sign in or learn about subscription options.pp. 6 pp.
by P. Golani, P.A. Beerel
Low Power System Design
A low power lookup technique for multi-hashing network applicationsFull-text access may be available. Sign in or learn about subscription options.pp. 6 pp.
by I. Kaya, T. Kocak
Low Power System Design
A Low Power Pipelined Maximum Likelihood Detector for 4x4 QPSK MIMO Wireless Communication SystemsFull-text access may be available. Sign in or learn about subscription options.pp. 185-192
by J.H Han, A.T Erdogan, T. Arslan
System-on-Chip
Optimal periodical memory allocation for logic-in-memory image processorsFull-text access may be available. Sign in or learn about subscription options.pp. 6 pp.
by M. Hariyama, M. Kameyama, Y. Kobayashi
New nonvolatile FPGA concept using magnetic tunneling junctionFull-text access may be available. Sign in or learn about subscription options.pp. 6 pp.
by N. Bruchon, L. Torres, G. Sassatelli, G. Cambon
System-on-Chip
Connection-oriented multicasting in wormhole-switched networks on chipFull-text access may be available. Sign in or learn about subscription options.pp. 6 pp.
by Zhonghai Lu, Bei Yin, A. Jantsch
System-on-Chip
A virtual channel network-on-chip for GT and BE trafficFull-text access may be available. Sign in or learn about subscription options.pp. 6 pp.-6 pp.
by N. Kavaldjiev, G.J.M. Smit, P.G. Jansen, P.T. Wolkotte
System-on-Chip
Delay-insensitive on-chip communication link using low-swing simultaneous bidirectional signalingFull-text access may be available. Sign in or learn about subscription options.pp. 6 pp.
by E. Nigussie, J. Plosila, J. Isoaho
Nano Electronics
Nanowire addressing in the face of uncertaintyFull-text access may be available. Sign in or learn about subscription options.pp. 6 pp.
by E. Rachlin, J.E. Savage
Nano Electronics
Si nanocrystal MOSFET with silicon nitride tunnel insulator for high-rate random number generationFull-text access may be available. Sign in or learn about subscription options.pp. 6 pp.
by R. Ohba, D. Matsushita, K. Muraoka, S. Yasuda, T. Tanamoto, K. Uchida, S. Fujita
Nano Electronics
Finite state machine implementation with single-electron tunneling technologyFull-text access may be available. Sign in or learn about subscription options.pp. 5 pp.
by Jialin Mi, Chunhong Chen
Nano Electronics
PLAs in quantum-dot cellular automataFull-text access may be available. Sign in or learn about subscription options.pp. 6 pp.
by Xiaobo Sharon Hu, M. Crocker, M. Niemier, Minjun Yan, G. Bernstein
Reconfigurable System Design and Technologies
Dynamic hardware multiplexing: improving adaptability with a run time reconfiguration managerFull-text access may be available. Sign in or learn about subscription options.pp. 6 pp.
by P. Benoit, L. Torres, G. Sassatelli, M. Robert, G. Cambon, J. Becker
Reconfigurable System Design and Technologies
Regular routing architecture for a LUT-based MPGAFull-text access may be available. Sign in or learn about subscription options.pp. 6 pp.
by F.-J. Veredas, M. Scheppler, Bumei Zhai, H.-J. Pfleiderer
Reconfigurable System Design and Technologies
A new multilevel hierarchical MFPGA and its suitable configuration toolsFull-text access may be available. Sign in or learn about subscription options.pp. 6 pp.
by Z. Marrakchi, H. Mrabet, H. Mehrez
Ultra-low energy computing with noise: Energy performance probabilityFull-text access may be available. Sign in or learn about subscription options.pp. 6 pp.
by P. Korkmaz, B.E.S. Akgul, K.V. Palem
Reconfigurable System Design and Technologies
New non-volatile FPGA concept using Magnetic Tunneling JunctionFull-text access may be available. Sign in or learn about subscription options.pp. 269-276
by Nicolas Bruchon, Lionel Torres, Gilles Sassatelli, Gaston Cambon
Complexity and System Organization
Profile directed instruction cache tuning for embedded systemsFull-text access may be available. Sign in or learn about subscription options.pp. 6 pp.
by K. Vivekanandarajah, T. Srikanthan, C.T. Clarke
Complexity and System Organization
Complexity and low power issues for on-chip interconnections in MPSoC system level designFull-text access may be available. Sign in or learn about subscription options.pp. 6 pp.
by Y. Sheynin, E. Suvorova, F. Shutenko
Complexity and System Organization
Fast configuration of an energy-efficient branch predictorFull-text access may be available. Sign in or learn about subscription options.pp. 6 pp.
by P. Hallschmid, R. Saleh
Complexity and System Organization
Exploiting software pipelining for network-on-chip architecturesFull-text access may be available. Sign in or learn about subscription options.pp. 6 pp.
by Feihui Li, M. Kandemir, I. Kolcu
System Level and Circuit Analysis
An efficient algorithm for the analysis of cyclic circuitsFull-text access may be available. Sign in or learn about subscription options.pp. 6 pp.
by O. Neiroukh, S.A. Edwards, X. Song
Performance and power analysis of globally asynchronous locally synchronous multiprocessor systemsFull-text access may be available. Sign in or learn about subscription options.pp. 6 pp.-6 pp.
by Zhiyi Yu, B.M. Baas
System Level and Circuit Analysis
Improving system level design space exploration by incorporating SAT-solvers into multi-objective evolutionary algorithmsFull-text access may be available. Sign in or learn about subscription options.pp. 6 pp.
by T. Schlichter, M. Lukasiewycz, C. Haubelt, J. Teich
System Level Design
Optimisation of the SHA-2 family of hash functions on FPGAsFull-text access may be available. Sign in or learn about subscription options.pp. 6 pp.
by R.P. McEvoy, F.M. Crowe, C.C. Murphy, W.P. Marnane
System Level Design
A novel approach to performance-oriented datapath allocation and floorplanningFull-text access may be available. Sign in or learn about subscription options.pp. 6 pp.
by V. Sundaresan, R. Vemuri
System Level Design
CHESS: a comprehensive tool for CDFG extraction and synthesis of low power designs from VHDLFull-text access may be available. Sign in or learn about subscription options.pp. 6 pp.
by N. Ranganathan, R. Namballa, N. Hanchate
A low-power 2D bypassing multiplier using 0.35 μm CMOS technologyFull-text access may be available. Sign in or learn about subscription options.pp. 4 pp.
by Chua-Chin Wang, Gang-Neng Sung
System Level Design
System exploration of SystemC designsFull-text access may be available. Sign in or learn about subscription options.pp. 6 pp.
by C. Genz, R. Drechsler
Power Aware VLSI Design
Reliability-aware SOC voltage islands partition and floorplanFull-text access may be available. Sign in or learn about subscription options.pp. 6 pp.
by Shengqi Yang, W. Wolf, N. Vijaykrishnan, Yuan Xie
Effect of glitches on the efficiency of components' region-constrained placement as a fast approach to reduce FPGA's dynamic power consumptionFull-text access may be available. Sign in or learn about subscription options.pp. 2 pp.
by S.E. Esmaeili, N.I. Khachab, M.Y. Ghannam
Power Aware VLSI Design
Ultra-Low Energy Computing with Noise: Energy-Performance-Probability Trade-offsFull-text access may be available. Sign in or learn about subscription options.pp. 349-354
by Pinar Korkrnaz, Bilge E. S. Akgul, Krishna V. Palem
Power Aware VLSI Design
Delay and energy efficient data transmission for on-chip busesFull-text access may be available. Sign in or learn about subscription options.pp. 6 pp.
by M. Mutyam, M. Eze, N. Vijaykrishnan, Yuan Xie
Power Aware VLSI Design
Power-oriented delay budgeting for combinational circuitsFull-text access may be available. Sign in or learn about subscription options.pp. 4 pp.
by Jialin Mi, Chunhong Chen
VLSI Circuits and Optimization
Routing-tree construction with concurrent performance, power and congestion optimizationFull-text access may be available. Sign in or learn about subscription options.pp. 6 pp.
by C. Alkan, T. Chen
VLSI Circuits and Optimization
Clock gated static pulsed flip-flop (CGSPFF) in sub 100 nm technologyFull-text access may be available. Sign in or learn about subscription options.pp. 5 pp.
by A.S. Seyedi, S.H. Rasouli, A. Amirabadi, A. Afzali-Kusha
VLSI Circuits and Optimization
Performance and Power Analysis of Globally Asynchronous Locally Synchronous Multi-Processor SystemsFull-text access may be available. Sign in or learn about subscription options.pp. 378-383
by Zhiyi Yu, Bevan M. Baas
VLSI Circuits and Optimization
Implementing register files for high-performance microprocessors in a die-stacked (3D) technologyFull-text access may be available. Sign in or learn about subscription options.pp. 6 pp.
by K. Puttaswamy, G.H. Loh
VLSI Circuits and Technologies
Leakage-aware SPM managementFull-text access may be available. Sign in or learn about subscription options.pp. 6 pp.-6 pp.
by Guangyu Chen, Feihui Li, O. Ozturk, Guilin Chen, M. Kandemir, I. Kolcu
VLSI Circuits and Technologies
Dependability analysis of nano-scale FinFET circuitsFull-text access may be available. Sign in or learn about subscription options.pp. 6 pp.
by Feng Wang, Yuan Xie, K. Bernstein, Yan Luo
VLSI Circuits and Technologies
A Low-Power 2-Dimensional Bypassing Multiplier Using 0.35 um CMOS TechnologyFull-text access may be available. Sign in or learn about subscription options.pp. 405-410
by Chua-Chin Wang, Gang-Neng Sung
Poster Papers
Multi-level buffer block planning and buffer insertion for large design circuitsFull-text access may be available. Sign in or learn about subscription options.pp. 5 pp.
by A. Jahanian, M.S. Zamani
Poster Papers
Effect of Glitches on the Efficiency of Components? Region-Constrained Placement as a Fast Approach to Reduce FPGA?s Dynamic Power ConsumptionFull-text access may be available. Sign in or learn about subscription options.pp. 416-417
by Seyed E. Esmaeili, Nabil I. Khachab, Moustafa Y. Ghannam
Poster Papers
Towards a faster simulation of SystemC designsFull-text access may be available. Sign in or learn about subscription options.pp. 2 pp.-2 pp.
by A. Habibi, H. Moinudeen, A. Samarah, S. Tahar
Poster Papers
An optimized BIST architecture for FPGA look-up table testingFull-text access may be available. Sign in or learn about subscription options.pp. 2 pp.
by M.S. Yarandi, A. Alaghi, Z. Navabi
Poster Papers
Variation aware placement for FPGAsFull-text access may be available. Sign in or learn about subscription options.pp. 2 pp.
by S. Srinivasan, V. Narayanan
Poster Papers
A regular layout approach for ASICsFull-text access may be available. Sign in or learn about subscription options.pp. 2 pp.
by C. Menezes, C. Meinhard, R. Reis, R. Tavares
Poster Papers
Evaluating the impact of data encoding techniques on the power consumption in networks-on-chipFull-text access may be available. Sign in or learn about subscription options.pp. 2 pp.
by J.C.S. Palma, L.S. Indrusiak, F.G. Moraes, A.G. Ortiz, M. Glesner, R.A.L. Reis
Poster Papers
Dual-mode high-speed low-energy binary additionFull-text access may be available. Sign in or learn about subscription options.pp. 2 pp.
by J. Grad, J.E. Stine
Poster Papers
A flexible architecture for block turbo decoders using BCH or Reed-Solomon components codesFull-text access may be available. Sign in or learn about subscription options.pp. 2 pp.
by E. Piriou, C. Jego, P. Adde, M. Jezequel
Poster Papers
Transparent management of reconfigurable hardware in embedded operating systemsFull-text access may be available. Sign in or learn about subscription options.pp. 2 pp.
by K. Kociuszkiewicz, F. Morgan, K. Kepa
Poster Papers
An open-source tool for simulation of partially reconfigurable systems using SystemCFull-text access may be available. Sign in or learn about subscription options.pp. 2 pp.-2 pp.
by A.V. de Brito, E.U.K. Melcher, W. Rosas
Poster Papers
Partial and dynamic reconfiguration of FPGAs: a top down design methodology for an automatic implementationFull-text access may be available. Sign in or learn about subscription options.pp. 2 pp.
by F. Berthelot, F. Nouvel
Poster Papers
Self-timed thermally-aware circuitsFull-text access may be available. Sign in or learn about subscription options.pp. 2 pp.
by D. Fang, F. Akopyan, R. Manohar
Poster Papers
A new protocol stack model for network on chipFull-text access may be available. Sign in or learn about subscription options.pp. 3 pp.
by M. Dehyadgari, M. Nickray, A. Afzali-kusha, Z. Navabi
Poster Papers
A robust synchronizerFull-text access may be available. Sign in or learn about subscription options.pp. 2 pp.
by Jun Zhou, D. Kinniment, G. Russell, A. Yakovlev
Poster Papers
Low power layered space-time channel detector architecture for MIMO systemsFull-text access may be available. Sign in or learn about subscription options.pp. 2 pp.
by T. Takahashi, A.T. Erdogan, T. Arslan, J.H. Han
Poster Papers
Sensor-driven power management: enhancing performance and reliability of autonomously powered systemsFull-text access may be available. Sign in or learn about subscription options.pp. 2 pp.
by J. Haid, D. Scheiblhofer
Poster Papers
Reducing memory requirements through task recomputation in embedded multi-CPU systemsFull-text access may be available. Sign in or learn about subscription options.pp. 2 pp.
by H. Koc, S. Tosun, O. Ozturk, M. Kandemir
Poster Papers
Compiler-directed management of leakage power in software-managed memoriesFull-text access may be available. Sign in or learn about subscription options.pp. 2 pp.-2 pp.
by G. Chen, M. Li, M. Kandemir, O. Ozturk, I. Demirkiran
Poster Papers
A parallel architecture for hardware face detectionFull-text access may be available. Sign in or learn about subscription options.pp. 2 pp.
by T. Theocharides, N. Vijaykrishnan, M.J. Irwin
Poster Papers
A VLSI GFP frame delineation circuitFull-text access may be available. Sign in or learn about subscription options.pp. 2 pp.
by C. Toal, S. Sezer, Xin Yang
Poster Papers
Effects of parameter variations and crosstalk noise on H-tree clock distribution networksFull-text access may be available. Sign in or learn about subscription options.pp. 2 pp.
by I. Chanodia, D. Velenis
Author Index
Author indexFreely available from IEEE.pp. 459-459
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