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2008 IEEE Computer Society Annual Symposium on VLSI

Apr. 7 2008 to Apr. 9 2008

ISBN: 978-0-7695-3170-0

Table of Contents

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Table of contentsFreely available from IEEE.pp. v-xii
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[Publisher's information]Freely available from IEEE.pp. 518
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Compensating Algorithmic-Loop Performance Degradation in Asynchronous Circuits Using Hardware Multi-threadingFull-text access may be available. Sign in or learn about subscription options.pp. 507-510
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Symposium CommitteesFreely available from IEEE.pp. xiv-xvi
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Title Page iFreely available from IEEE.pp. i
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Title Page iiiFreely available from IEEE.pp. iii
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Title Page iv - Copyright PageFreely available from IEEE.pp. iv
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Message from the General and Program ChairsFreely available from IEEE.pp. xiii
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Adaptive Reliable Chips - Reconfigurable Computing in the Nano EraFull-text access may be available. Sign in or learn about subscription options.pp. 1-2
by Jürgen Becker
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Emerging Concepts in Non-volatile Memory Technologies - Era of Resistance Switching MemoriesFull-text access may be available. Sign in or learn about subscription options.pp. 3-3
by Chrisophe Muller
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Arithmetic Data Path Optimization Using Borrow-Save RepresentationFull-text access may be available. Sign in or learn about subscription options.pp. 4-9
by Sophie Belloeil, Roselyne Chotin-Avot, Habib Mehrez
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Design of Robust and High-Performance 1-Bit CMOS Full Adder for Nanometer DesignFull-text access may be available. Sign in or learn about subscription options.pp. 10-15
by Omid Kavehei, Mostafa Rahimi Azghadi, Keivan Navi, Amir-Pasha Mirbaha
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Benchmarking Domain Specific Processors: A Case Study of Evaluating a Smart Card Processor DesignFull-text access may be available. Sign in or learn about subscription options.pp. 16-21
by Zhonglei Wang, Thomas Wild, Stefan R?, Bernhard Lippmann
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Determining the Optimal Number of Islands in Power Islands SynthesisFull-text access may be available. Sign in or learn about subscription options.pp. 22-27
by Deniz Dal, Nazanin Mansouri
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Defect Tolerance Inspired by Artificial EvolutionFull-text access may be available. Sign in or learn about subscription options.pp. 28-33
by Asbjoern Djupdal, Pauline C. Haddow
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Reliability of n-Bit Nanotechnology AdderFull-text access may be available. Sign in or learn about subscription options.pp. 34-39
by Ismo H?nninen, Jarmo Takala
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Spintronic Device Based Non-volatile Low Standby Power SRAMFull-text access may be available. Sign in or learn about subscription options.pp. 40-45
by Weisheng Zhao, Eric Belhaire, Claude Chappert, Pascale Mazoyer
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Application of Bottom-Up Methodology to RTW VCOFull-text access may be available. Sign in or learn about subscription options.pp. 46-50
by F. Ben Abdeljelil, B. Nicolle, W. Tatinian, L. Carpineto, J. Oudinot, G. Jacquemod
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A Closed-Loop Architecture with Digital Output for Convective AccelerometersFull-text access may be available. Sign in or learn about subscription options.pp. 51-56
by O. Leman, L. Latorre, F. Mailly, P. Nouet
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A CMOS Multi-sensor System for 3D Orientation DeterminationFull-text access may be available. Sign in or learn about subscription options.pp. 57-62
by B. Alandry, N. Dumas, L. Latorre, F. Mailly, P. Nouet
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FSMD Partitioning for Low Power Using ILPFull-text access may be available. Sign in or learn about subscription options.pp. 63-68
by Nainesh Agarwal, Nikitas Dimopoulos
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Uncriticality-Directed Low-Power Instruction SchedulingFull-text access may be available. Sign in or learn about subscription options.pp. 69-74
by Shingo Watanabe, Toshinori Sato
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Smart-NICs: Power Proxying for Reduced Power Consumption in Network Edge DevicesFull-text access may be available. Sign in or learn about subscription options.pp. 75-80
by Karthikeyan Sabhanatarajan, Ann Gordon-Ross, Mark Oden, Mukund Navada, Alan George
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BTB Access Filtering: A Low Energy and High Performance DesignFull-text access may be available. Sign in or learn about subscription options.pp. 81-86
by Shuai Wang, Jie Hu, Sotirios G. Ziavras
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A Novel Multiple Core Co-processor Architecture for Efficient Server-Based Public Key Cryptographic ApplicationsFull-text access may be available. Sign in or learn about subscription options.pp. 87-92
by Ralf Laue, H. Gregor Molter, Felix Rieder, Sorin A. Huss, Kartik Saxena
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System Level Design Space Exploration for Multiprocessor System on ChipFull-text access may be available. Sign in or learn about subscription options.pp. 93-98
by Issam Maalej, Guy Gogniat, Jean Luc Philippe, Mohamed Abid
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A Novel System-Level On-Chip Resource Allocation Method for Manycore ArchitecturesFull-text access may be available. Sign in or learn about subscription options.pp. 99-104
by Theocharis Theocharides, Maria K. Michael, Marios Polycarpou, Ajit Dingankar
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MPI-Based Adaptive Task Migration Support on the HS-Scale SystemFull-text access may be available. Sign in or learn about subscription options.pp. 105-110
by N. Saint-Jean, P. Benoit, G. Sassatelli, L. Torres, M. Robert
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Low Power High Performance Digitally Assisted Pipelined ADCFull-text access may be available. Sign in or learn about subscription options.pp. 111-116
by Bahar Jalali Farahani, Anand Meruva
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A Novel Low-Power Clock Skew Compensation CircuitFull-text access may be available. Sign in or learn about subscription options.pp. 117-121
by Rong Ji, Liang Chen, Gang Luo, Xianjun Zeng, Junfeng Zhang, Yingjie Feng
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High Speed Ultra Low Voltage CMOS inverterFull-text access may be available. Sign in or learn about subscription options.pp. 122-127
by Yngvar Berg, Omid Mirmotahari, Johannes Goplen Lomsdalen, Snorre Aunet
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A Novel Encoding Scheme for Delay and Energy Minimization in VLSI Interconnects with Built-In Error DetectionFull-text access may be available. Sign in or learn about subscription options.pp. 128-133
by Lingamneni Avinash, M. Kirthi Krishna, M. B. Srinivas
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Process Algebra Based SoC Test Scheduling for Test Time MinimizationFull-text access may be available. Sign in or learn about subscription options.pp. 134-138
by Jingbo Shao, Guangsheng Ma, Zhi Yang, Ruixue Zhang
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Improving the Test of NoC-Based SoCs with Help of Compression SchemesFull-text access may be available. Sign in or learn about subscription options.pp. 139-144
by Julien Dalmasso, ?rika Cota, Marie-Lise Flottes, Bruno Rouzeyre
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A Novel System on Chip (SoC) Test SolutionFull-text access may be available. Sign in or learn about subscription options.pp. 145-150
by Michael Higgins, Ciaran MacNamee, Brendan Mullane
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Testing Skew and Logic Faults in SoC InterconnectsFull-text access may be available. Sign in or learn about subscription options.pp. 151-156
by N?stor Hern?ndez, Victor Champac
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A Programmable Frequency Divider in 0.18 um(micro-meter) CMOS LibraryFull-text access may be available. Sign in or learn about subscription options.pp. 157-161
by Qingsheng Hu, Hua-An Zhao, Chen Liu
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Energy Recovery from High-Frequency Clocks Using DC-DC ConvertersFull-text access may be available. Sign in or learn about subscription options.pp. 162-167
by M. Alimadadi, S. Sheikhaei, G. Lemieux, S. Mirabbasi, W. Dunford, P. Palmer
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Improving Bandwidth while Managing Phase Noise and Spurs in Fractional-N PLLFull-text access may be available. Sign in or learn about subscription options.pp. 168-172
by Xiao Pu, Axel Thomsen, Jacob Abraham
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Systematic HDL Design of a S-? Fractional-N Phase-Locked Loop for Wireless ApplicationsFull-text access may be available. Sign in or learn about subscription options.pp. 173-178
by Ahmed El Oualkadi, Denis Flandre
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Impact of Technology Scaling on Digital Subthreshold CircuitsFull-text access may be available. Sign in or learn about subscription options.pp. 179-184
by David Bol, Renaud Ambroise, Denis Flandre, Jean-Didier Legat
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Low Standby Power and Robust FinFET Based SRAM DesignFull-text access may be available. Sign in or learn about subscription options.pp. 185-190
by Behzad Ebrahimi, Saeed Zeinolabedinzadeh, Ali Afzali-Kusha
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CMOS Control Enabled Single-Type FET NASICFull-text access may be available. Sign in or learn about subscription options.pp. 191-196
by Pritish Narayanan, Michael Leuchtenburg, Teng Wang, Csaba Andras Moritz
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A Generic Design for Encoding and Decoding Variable Length Codes in Multi-codec Video Processing EnginesFull-text access may be available. Sign in or learn about subscription options.pp. 197-202
by V. K. Prasad Arava, Manhwee Jo, HyoukJoong Lee, Kiyoung Choi
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Transforms and Quantization in the High-Throughput H.264/AVC Encoder Based on Advanced Mode SelectionFull-text access may be available. Sign in or learn about subscription options.pp. 203-208
by Grzegorz Pastuszak
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Communication Centric Modelling of System on Chip Devices Targeting Multi-standard Telecommunication ApplicationsFull-text access may be available. Sign in or learn about subscription options.pp. 209-214
by Ali Ahmadinia, Balal Ahmad, Tughrul Arslan
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Performance Improvement of Physical Retiming with Shortcut InsertionFull-text access may be available. Sign in or learn about subscription options.pp. 215-220
by Adel Dokhanchi, Mostafa Rezvani, Ali Jahanian, Morteza Saheb Zamani
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A Low-Power Buffered Tree Construction Algorithm Aware of Supply Voltage VariationFull-text access may be available. Sign in or learn about subscription options.pp. 221-226
by Yibo Wang, Yici Cai, Xianlong Hong
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A New Clock Mesh Buffer Sizing Methodology for Skew and Power ReductionFull-text access may be available. Sign in or learn about subscription options.pp. 227-232
by Gustavo Wilke, Ricardo Reis
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An Efficient Method to Estimate Crosstalk after Placement Incorporating a Reduction SchemeFull-text access may be available. Sign in or learn about subscription options.pp. 233-238
by Arash Mehdizadeh, Morteza Saheb Zamani, H. Shafiei
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A Real Case of Significant Scan Test Cost ReductionFull-text access may be available. Sign in or learn about subscription options.pp. 239-244
by Selina Sha, Bruce Swanson
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A Network Based Functional Verification Method of IEEE 1394a PHY CoreFull-text access may be available. Sign in or learn about subscription options.pp. 245-250
by Colin Yu Lin, Song Cao, Junshe An, Fei Han, Qifei Fan
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Cohesive Coverage Management for Simulation and Formal Property VerificationFull-text access may be available. Sign in or learn about subscription options.pp. 251-256
by Aritra Hazra, Ansuman Banerjee, Srobona Mitra, Pallab Dasgupta, Partha Pratim Chakrabarti, Chunduri Rama Mohan
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Scalable Calculation of Logical Masking Effects for Selective Hardening Against Soft ErrorsFull-text access may be available. Sign in or learn about subscription options.pp. 257-262
by Ilia Polian, Sudhakar M. Reddy, Bernd Becker
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Memory Power Modeling - A Novel ApproachFull-text access may be available. Sign in or learn about subscription options.pp. 263-268
by Ajit Gupte, Mohit Sharma, Gaurav Varshney, Lakshmikantha Holla, Parvinder Rana, Udayakumar H.
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Integrated Power-Gating and State Assignment for Low Power FSM SynthesisFull-text access may be available. Sign in or learn about subscription options.pp. 269-274
by Sambhu Nath Pradhan, M. Tilak Kumar, Santanu Chattopadhyay
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Efficient High-Level Power Estimation for Multi-standard Wireless SystemsFull-text access may be available. Sign in or learn about subscription options.pp. 275-280
by Ali Ahmadinia, Balal Ahmad, Tughrul Arslan
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Modeling and Optimization of Switching Power Dissipation in Static CMOS CircuitsFull-text access may be available. Sign in or learn about subscription options.pp. 281-285
by Adnan Kabbani
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Core Allocation and Relocation Management for a Self Dynamically Reconfigurable ArchitectureFull-text access may be available. Sign in or learn about subscription options.pp. 286-291
by M. Morandi, M. Novati, M. D. Santambrogio, D. Sciuto
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SeReCon: A Secure Dynamic Partial Reconfiguration ControllerFull-text access may be available. Sign in or learn about subscription options.pp. 292-297
by Krzysztof Kepa, Fearghal Morgan, Krzysztof Kosciuszkiewicz, Tomasz Surmacz
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GePaRD - A High-Level Generation Flow for Partially Reconfigurable DesignsFull-text access may be available. Sign in or learn about subscription options.pp. 298-303
by Maik Boden, Thomas Fiebig, Markus Reiband, Peter Reichel, Steffen R?
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Exploitation of the External JTAG Interface for Internally Controlled Configuration Readback and Self-Reconfiguration of Spartan 3 FPGAsFull-text access may be available. Sign in or learn about subscription options.pp. 304-309
by Katarina Paulsson, Ulrich Viereck, Michael H?, J? Becker
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Statistical Sizing of an eSRAM Dummy Bitline Driver for Read Margin Improvement in the Presence of Variability AspectsFull-text access may be available. Sign in or learn about subscription options.pp. 310-315
by M. Yap San Min, P. Maurine, M. Bastian, M. Robert
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Setup and Hold Timing Violations Induced by Process Variations, in a Digital MultiplierFull-text access may be available. Sign in or learn about subscription options.pp. 316-321
by B. Rebaud, M. Belleville, C. Bernard, Z. Wu, M. Robert, P. Maurine, N. Azemard
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Characterisation of FPGA Clock VariabilityFull-text access may be available. Sign in or learn about subscription options.pp. 322-328
by Pete Sedcole, Justin S. Wong, Peter Y. K. Cheung
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A Fuzzy Approach for Variation Aware Buffer Insertion and Driver SizingFull-text access may be available. Sign in or learn about subscription options.pp. 329-334
by V. Mahalingam, N. Ranganathan
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Flow Maximization for NoC Routing AlgorithmsFull-text access may be available. Sign in or learn about subscription options.pp. 335-340
by Ying-Cherng Lan, Michael C. Chen, Alan P. Su, Yu-Hen Hu, Sao-Jie Chen
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Deadlock-Free Multicast Routing Algorithm for Wormhole-Switched Mesh Networks-on-ChipFull-text access may be available. Sign in or learn about subscription options.pp. 341-346
by Everton Alceu Carara, Fernando Gehm Moraes
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Hermes-GLP: A GALS Network on Chip Router with Power Control TechniquesFull-text access may be available. Sign in or learn about subscription options.pp. 347-352
by Julian Pontes, Matheus Moreira, Rafael Soares, Ney Calazans
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Adaptive Neuron Activation Function with FGMOS Based Operational Transconductance AmplifierFull-text access may be available. Sign in or learn about subscription options.pp. 353-356
by V. Suresh Babu, Rose Katharine A. A., M. R. Baiju
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A Versatile Linear Insertion Sorter Based on a FIFO SchemeFull-text access may be available. Sign in or learn about subscription options.pp. 357-362
by Roberto Perez-Andrade, Rene Cumplido, Fernando Martin Del Campo, Claudia Feregrino-Uribe
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Improving Energy Efficiency of Configurable Caches via Temperature-Aware Configuration SelectionFull-text access may be available. Sign in or learn about subscription options.pp. 363-368
by Hamid Noori, Maziar Goudarzi, Koji Inoue, Kazuaki Murakami
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Thermal-Aware Placement of Standard Cells and Gate Arrays: Studies and ObservationsFull-text access may be available. Sign in or learn about subscription options.pp. 369-374
by Prasun Ghosal, Tuhina Samanta, Hafizur Rahaman, Parthasarathi Dasgupta
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Temperature-Aware Distributed Run-Time Optimization on MP-SoC Using Game TheoryFull-text access may be available. Sign in or learn about subscription options.pp. 375-380
by Diego Puschini, Fabien Clermidy, Pascal Benoit, Gilles Sassatelli, Lionel Torres
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Standard Cell Like Via-Configurable Logic Block for Structured ASICsFull-text access may be available. Sign in or learn about subscription options.pp. 381-386
by Mei-Chen Li, Hui-Hsiang Tung, Chien-Chung Lai, Rung-Bin Lin
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SDVM^R: A Scalable Firmware for FPGA-Based Multi-core Systems-on-ChipFull-text access may be available. Sign in or learn about subscription options.pp. 387-392
by Andreas Hofmann, Klaus Waldschmidt
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Fast Hardware Upper-Bound Power Estimation for a Novel FPGA-Based HW/SW Partitioning SchemeFull-text access may be available. Sign in or learn about subscription options.pp. 393-398
by M. B. Abdelhalim, S. E.-D. Habib
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FPGA-Based Circuit Model Emulation of Quantum AlgorithmsFull-text access may be available. Sign in or learn about subscription options.pp. 399-404
by Mahdi Aminian, Mehdi Saeedi, Morteza Saheb Zamani, Mehdi Sedighi
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Petri Net Based Rapid Prototyping of Digital Complex SystemFull-text access may be available. Sign in or learn about subscription options.pp. 405-410
by David Andreu, Guillaume Souquet, Thierry Gil
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Using Higher Levels of Abstraction for Solving Optimization Problems by Boolean SatisfiabilityFull-text access may be available. Sign in or learn about subscription options.pp. 411-416
by Robert Wille, Daniel Gro?e, Mathias Soeken, Rolf Drechsler
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A Multi-objective Genetic Algorithm for Design Space Exploration in High-Level SynthesisFull-text access may be available. Sign in or learn about subscription options.pp. 417-422
by Fabrizio Ferrandi, Pier Luca Lanzi, Daniele Loiacono, Christian Pilato, Donatella Sciuto
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Simultaneous Scheduling, Allocation, Binding, Re-ordering, and Encoding for Crosstalk Pattern Minimization during High Level SynthesisFull-text access may be available. Sign in or learn about subscription options.pp. 423-428
by Hariharan Sankaran, Srinivas Katkoori
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Efficient Realization of Strongly Indicating Function BlocksFull-text access may be available. Sign in or learn about subscription options.pp. 429-432
by P. Balasubramanian, D. A. Edwards
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Virtual Point-to-Point Links in Packet-Switched NoCsFull-text access may be available. Sign in or learn about subscription options.pp. 433-436
by Mehdi Modarressi, Hamid Sarbazi-Azad, Arash Tavakkol
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Controlling Ground Bounce Noise in Power Gating Scheme for System-on-a-ChipFull-text access may be available. Sign in or learn about subscription options.pp. 437-440
by Masud H. Chowdhury, Juliana Gjanci, Pervez Khaled
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A Web Server Based Edge Detector Implementation in FPGAFull-text access may be available. Sign in or learn about subscription options.pp. 441-446
by Sunil Shukla, Neil W. Bergmann, J? Becker
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Cache Power Reduction in Presence of Within-Die Delay Variation Using Spare WaysFull-text access may be available. Sign in or learn about subscription options.pp. 447-450
by Maziar Goudarzi, Tadayuki Matsumura, Tohru Ishihara
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In Situ Design of Register OperationsFull-text access may be available. Sign in or learn about subscription options.pp. 451-454
by Serge Burckel, Emeric Gioan
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An Efficient Motion Adaptive De-interlacing and Its VLSI Architecture DesignFull-text access may be available. Sign in or learn about subscription options.pp. 455-458
by Hongbin Sun, Nanning Zheng, Chenyang Ge, Dong Wang, Pengju Ren
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Raising the Level of Abstraction for the Timing Verification of System-on-ChipsFull-text access may be available. Sign in or learn about subscription options.pp. 459-462
by Rupsa Chakraborty, Dipanwita Roy Chowdhury
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Power Modeling in SystemC at Transaction Level, Application to a DVFS ArchitectureFull-text access may be available. Sign in or learn about subscription options.pp. 463-466
by Hugo Lebreton, Pascal Vivet
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Simultaneous Gate Sizing and Skew Scheduling to Statistical Yield ImprovementFull-text access may be available. Sign in or learn about subscription options.pp. 467-470
by Minoo Mirsaeedi, Morteza Saheb Zamani, Mehdi Saeedi
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Shared-PPRM: A Memory-Efficient Representation for Boolean Reversible FunctionsFull-text access may be available. Sign in or learn about subscription options.pp. 471-474
by Yasaman Sanaee, Mehdi Saeedi, Morteza Saheb Zamani
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NoC Power Estimation at the RTL Abstraction LevelFull-text access may be available. Sign in or learn about subscription options.pp. 475-478
by Guilherme Guindani, Cezar Reinbrecht, Thiago Raupp, Ney Calazans, Fernando Gehm Moraes
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Design of Fractal Image Compression on SOCFull-text access may be available. Sign in or learn about subscription options.pp. 479-482
by A. Jedidi, B. Rejeb, M. Abid
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A Novel and Scalable RSA Cryptosystem Based on 32-Bit Modular MultiplierFull-text access may be available. Sign in or learn about subscription options.pp. 483-486
by Jin-Hua Hong, Wen-Jie Li
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A Neural Stimulator Output Stage for Dodecapolar ElectrodesFull-text access may be available. Sign in or learn about subscription options.pp. 487-490
by F. Soulier, J.-B. Lerat, L. Gouyet, S. Bernard, G. Cath?bras
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Applying UML Interactions and Actor-Oriented Simulation to the Design Space Exploration of Network-on-Chip InterconnectsFull-text access may be available. Sign in or learn about subscription options.pp. 491-494
by Leandro Soares Indrusiak, Luciano Ost, Leandro M?ller, Fernando Moraes, Manfred Glesner
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Finding the Best Compromise in Compiling Compound Loops to VerilogFull-text access may be available. Sign in or learn about subscription options.pp. 495-498
by Yosi Ben-Asher, Eddie Shochat
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An Auto-adaptation Method for Dynamically Reconfigurable System-on-ChipFull-text access may be available. Sign in or learn about subscription options.pp. 499-502
by Xun Zhang, Hassan Rabah, Serge Weber
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