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13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems

April 14 2010 to April 16 2010

Vienna

Table of Contents

Papers
Symposium CommitteesFreely available from IEEE.pp. 1-1
Papers
Table of contentsFreely available from IEEE.pp. 1-6
Papers
ForewordFreely available from IEEE.pp. 1-1
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[Copyright notice]Freely available from IEEE.pp. 1-1
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Self-repairing and tuning reconfigurable electronics for spaceFull-text access may be available. Sign in or learn about subscription options.pp. 1
by Didier Keymeulen
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Safety features of SoCs: How can they be re-used?Full-text access may be available. Sign in or learn about subscription options.pp. 2
by Davide Appello
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Asynchronous design, Quo Vadis?Full-text access may be available. Sign in or learn about subscription options.pp. 3
by Alex Yakovlev
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Formal verification meets robustness checking — Techniques and challengesFull-text access may be available. Sign in or learn about subscription options.pp. 4
by Rolf Drechsler, Gorschwin Fey
Evolutionary circuit design: TutorialFull-text access may be available. Sign in or learn about subscription options.pp. 5-5
by Lukáš Sekanina
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Advanced embedded memory testing: Reducing the defect per million level at lower test costFull-text access may be available. Sign in or learn about subscription options.pp. 7
by Said Hamdioui, Ad J. van de Goor
Ensuring high testability without degrading security: Embedded tutorial on “test and security”Full-text access may be available. Sign in or learn about subscription options.pp. 6-6
by G. Di Natale, M.-L. Flottes, B. Rouzeyre
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Noise determination of a current conveyor in an inverting voltage amplifier configurationFull-text access may be available. Sign in or learn about subscription options.pp. 12-15
by S. Siskos
Automated simulation-based verification of power requirements for Systems-on-ChipsFull-text access may be available. Sign in or learn about subscription options.pp. 8-11
by Christoph Trummer, Christoph M. Kirchsteiger, Christian Steger, Reinhold Weiß, Markus Pistauer, Damian Dalton
Utilizing the Bulk-driven technique in analog circuit designFull-text access may be available. Sign in or learn about subscription options.pp. 16-19
by Fabian Khateb, Dalibor Biolek, Nabhan Khatib, Jiří Vávra
Instruction reliability analysis for embedded processorsFull-text access may be available. Sign in or learn about subscription options.pp. 20-23
by Ali Azarpeyvand, Mostafa E. Salehi, Farshad Firouzi, Amir Yazdanbakhsh, Sied Mehdi Fakhraie
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Automated SEU fault emulation using partial FPGA reconfigurationFull-text access may be available. Sign in or learn about subscription options.pp. 24-27
by Uros Legat, Anton Biasizzo, Franc Novak
Low-cost fault tolerance on the ALU in simple pipelined processorsFull-text access may be available. Sign in or learn about subscription options.pp. 28-31
by Nguyen Minh Huu, Bruno Robisson, Michel Agoyan, Nathalie Drach
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On the mitigation of SET broadening effects in integrated circuitsFull-text access may be available. Sign in or learn about subscription options.pp. 36-39
by Luca Sterpone, Niccolo Battezzati
Design of a single layer programmable Structured ASIC libraryFull-text access may be available. Sign in or learn about subscription options.pp. 32-35
by Thomas C. P. Chau, David W. L. Wu, Yan-Qing Ai, Brian P. W. Chan, Sam M. H. Ho, Oscar K. L. Lau, Steve C. L. Yuen, Kong-Pang Pun, Oliver C. S. Choy, Philip H. W. Leong
A software-based self-test and hardware reconfiguration solution for VLIW processorsFull-text access may be available. Sign in or learn about subscription options.pp. 40-43
by Tobias Koal, Heinrich Theodor Vierhaus
A low power low voltage mixer for 2.4GHz applications in CMOS-90nm technologyFull-text access may be available. Sign in or learn about subscription options.pp. 44-47
by Alberto Villegas, Diego Váquez, Adoración Rueda
Characterization of randomness sources in ring oscillator-based true random number generators in FPGAsFull-text access may be available. Sign in or learn about subscription options.pp. 48-53
by Boyan Valtchanov, Viktor Fischer, Alain Aubert, Florent Bernard
Efficient mapping of nondeterministic automata to FPGA for fast regular expression matchingFull-text access may be available. Sign in or learn about subscription options.pp. 54-59
by Jan Kor̆enek, Vlastimil Kos̆ar̆
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Software-based self-repair of statically scheduled superscalar data pathsFull-text access may be available. Sign in or learn about subscription options.pp. 66-71
by Mario Scholzel
Data compression in hardware — The Burrows-Wheeler approachFull-text access may be available. Sign in or learn about subscription options.pp. 60-65
by S. Arming, R. Fenkhuber, T. Handl
Built-in Clock Domain Crossing (CDC) test and diagnosis in GALS systemsFull-text access may be available. Sign in or learn about subscription options.pp. 72-77
by C. Leong, P. Machado, V. Bexiga, J. P. Teixeira, I. C. Teixeira, J. C. Silva, P. Lousã, J. Varela
A better-than-worst-case robustness measureFull-text access may be available. Sign in or learn about subscription options.pp. 78-83
by Stefan Frehse, Görschwin Fey, Rolf Drechsler
An integrated low power buck converter with a comparator controlled low-side switchFull-text access may be available. Sign in or learn about subscription options.pp. 84-87
by Reinhard Enne, Horst Zimmermann
A Build-In Self-Test technique for RF MixersFull-text access may be available. Sign in or learn about subscription options.pp. 88-92
by Lambros Dermentzoglou, Angela Arapoyanni, Yiorgos Tsiatouhas
Ultra low-voltage bidirectional current mirror using clocked semi-floating-gate transistorsFull-text access may be available. Sign in or learn about subscription options.pp. 93-98
by Yngvar Berg
Combining de-stressing and self repair for long-term dependable systemsFull-text access may be available. Sign in or learn about subscription options.pp. 99-104
by T. Koal, H. T. Vierhaus
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Exploration of the FlexRay signal integrity using a combined prototyping and simulation approachFull-text access may be available. Sign in or learn about subscription options.pp. 111-116
by Martin Krammer, Federico Clazzer, Eric Armengaud, Michael Karner, Christian Steger, Reinhold Weiss
Developing reconfigurable FIFOs to optimize power/performance of Voltage/Frequency Island-based networks-on-chipFull-text access may be available. Sign in or learn about subscription options.pp. 105-110
by Amir-Mohammad Rahmani, Pasi Liljeberg, Juha Plosila, Hannu Tenhunen
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Design — Time configurable processor basic structureFull-text access may be available. Sign in or learn about subscription options.pp. 119-120
by Filip Adamec, Tomas Fryza
Self-Adaptive mechanism for cache memory reliability improvementFull-text access may be available. Sign in or learn about subscription options.pp. 117-118
by Liviu Agnola, Mircea Vlădutiu, Mihai Udrescu
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A 65nm embedded low power SRAM compilerFull-text access may be available. Sign in or learn about subscription options.pp. 123-124
by Sheng Wu, Xiang Zheng, Zhiqiang Gao, Xiangqing He
Reconfigurable hardware objects for image processing on FPGAsFull-text access may be available. Sign in or learn about subscription options.pp. 121-122
by Jan Kloub, Petr Honzík, Martin Daněk
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Blind image deconvolution algorithm on NVIDIA CUDA platformFull-text access may be available. Sign in or learn about subscription options.pp. 125-126
by Tomas Mazanec, Antonin Hermanek, Jan Kamenicky
Partitioning methods for unicast/multicast traffic in 3D NoC architectureFull-text access may be available. Sign in or learn about subscription options.pp. 127-132
by Masoumeh Ebrahimi, Masoud Daneshtalab, Pasi Liljeberg, Hannu Tenhunen
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SystemC-AMS SDF model synthesis for exploration of heterogeneous architecturesFull-text access may be available. Sign in or learn about subscription options.pp. 133-138
by Andreas Popp, Andreas Herrholz, Kim Griittner, Yannick Le Moullec, Peter Koch, Wolfgang Nebel
A fault-tolerant and congestion-aware routing algorithm for Networks-on-ChipFull-text access may be available. Sign in or learn about subscription options.pp. 139-144
by Mojtaba Valinataj, Siamak Mohammadi, Juha Plosila, Pasi Liljeberg
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Current Sensing Completion Detection in deep sub-micron technologiesFull-text access may be available. Sign in or learn about subscription options.pp. 145-148
by Lukas Nagy, Viera Stopjakova
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Hardware accelerated pattern matching based on Deterministic Finite Automata with perfect hashingFull-text access may be available. Sign in or learn about subscription options.pp. 149-152
by Jan Kastil, Jan Korenek
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Combined matched filter and arbitrary interpolator for symbol timing synchronization in SDR receiversFull-text access may be available. Sign in or learn about subscription options.pp. 153-156
by Mehmood-ur-Rehman Awan, Peter Koch
A 3–5GHz UWB CMOS receiver with digital control techniqueFull-text access may be available. Sign in or learn about subscription options.pp. 157-160
by Bo Han, Mengmeng Liu, Ning Ge
Computation reduction for statistical analysis of the effect of nano-CMOS variability on asynchronous circuitsFull-text access may be available. Sign in or learn about subscription options.pp. 161-166
by Zheng Xie, Doug Edwards
Buffer-ring-based all-digital on-chip monitor for PMOS and NMOS process variability and aging effectsFull-text access may be available. Sign in or learn about subscription options.pp. 167-172
by Tetsuya Iizuka, Toru Nakura, Kunihiro Asada
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Modern fault tolerant architectures based on partial dynamic reconfiguration in FPGAsFull-text access may be available. Sign in or learn about subscription options.pp. 173-176
by Martin Straka, Jan Kastil, Zdenek Kotasek
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Testing analog electronic circuits using N-terminal networkFull-text access may be available. Sign in or learn about subscription options.pp. 177-180
by Piotr Kyziol, Jerzy Rutkowski, Damian Grzechca
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A low phase noise 20 GHz voltage control oscillator using 0.18-µm CMOS technologyFull-text access may be available. Sign in or learn about subscription options.pp. 185-188
by C. M. Yang, H. L. Kao, Y. C. Chang, M. T. Chen, H. M. Chang, C. H. Wu
The novel approach to wideband RFIC receivers in standard CMOS processFull-text access may be available. Sign in or learn about subscription options.pp. 181-184
by Libor Majer, Viera Stopjaková
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SREEP: Shift Register Equivalents Enumeration and Synthesis Program for secure scan designFull-text access may be available. Sign in or learn about subscription options.pp. 193-196
by Katsuya Fujiwara, Hideo Fujiwara, Marie Engelene J. Obien, Hideo Tamamoto
Tree-model based mapping for energy-efficient and low-latency Network-on-ChipFull-text access may be available. Sign in or learn about subscription options.pp. 189-192
by Bo Yang, Thomas Canhao Xu, Tero Säntti, Juha Plosila
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How to reduce size of a signature-based diagnostic dictionary used for testing of connectionsFull-text access may be available. Sign in or learn about subscription options.pp. 201-204
by Garbolino Tomasz, Gucwa Krzysztof, Hlawiczka Andrzej
A synthesis method to propagate false path information from RTL to gate levelFull-text access may be available. Sign in or learn about subscription options.pp. 197-200
by Satoshi Ohtake, Hiroshi Iwata, Hideo Fujiwara
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Highly linear down-conversion mixer in 65nm CMOS for a high supply voltage of 2.5VFull-text access may be available. Sign in or learn about subscription options.pp. 205-208
by Kurt Schweiger, Horst Zimmermann
A mixer-filter combination of a direct conversion receiver for DVB-H applications in 65nm CMOSFull-text access may be available. Sign in or learn about subscription options.pp. 209-212
by Heimo Uhrmann, Lukas Dörrer, Franz Kuttner, Kurt Schweiger, Horst Zimmermann
A comparison of low voltage LNA architectures designed for multistandard GNSS in two 90 nm CMOS technologiesFull-text access may be available. Sign in or learn about subscription options.pp. 213-216
by Jacek Grądzki, Tomasz Borejko, Witold A. Pleskacz
Intelligent IGBT driver concept for three-phase electric drive diagnosticsFull-text access may be available. Sign in or learn about subscription options.pp. 217-220
by B. Klima, J. Knobloch, M. Pochyla
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Theorem proving techniques for the formal verification of NoC communications with non-minimal adaptive routingFull-text access may be available. Sign in or learn about subscription options.pp. 221-224
by Amr Helmy, Laurence Pierre, Axel Jantsch
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NoGapCL: A flexible common language for processor hardware descriptionFull-text access may be available. Sign in or learn about subscription options.pp. 225-228
by Wenbiao Zhou, Per Karlstrom, Dake Liu
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Modeling temperature distribution in Networks-on-Chip using RC-circuitsFull-text access may be available. Sign in or learn about subscription options.pp. 229-232
by Andreas Tockhorn, Claas Cornelius, Hagen Saemrow, Dirk Timmermann
Enhancing pipelined processor architectures with fast autonomous recovery of transient faultsFull-text access may be available. Sign in or learn about subscription options.pp. 233-236
by Marcus Jeitler, Jakob Lechner, Andreas Steininger
Instruction set extensions for multi-threading in LEON3Full-text access may be available. Sign in or learn about subscription options.pp. 237-242
by M. Danek, L. Kafka, L. Kohout, J. Sykora
Wrapper design for a CDMA bus in SOCFull-text access may be available. Sign in or learn about subscription options.pp. 243-248
by T. Nikolić, M. Stojčev, Z. Stamenković
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Evaluation of Radix-2 and Radix-4 FFT processing on a reconfigurable platformFull-text access may be available. Sign in or learn about subscription options.pp. 249-254
by Waqar Hussain, Fabio Garzia, Jari Nurmi
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Evaluation of transition untestable faults using a multi-cycle capture test generation methodFull-text access may be available. Sign in or learn about subscription options.pp. 273-276
by Masayoshi Yoshimura, Hiroshi Ogawa, Toshinori Hosokawa, Koji Yamazaki
Using a CISC microcontroller to test embedded memoriesFull-text access may be available. Sign in or learn about subscription options.pp. 261-266
by Ad van de Goor, Said Hamdioui, Georgi Gaydadjiev
Memory elements based on minority-3 gates and inverters implemented in 90 nm CMOSFull-text access may be available. Sign in or learn about subscription options.pp. 267-272
by Snorre Aunet, Amir Hasanbegovic
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A time-to-digital converter using multi-phase-sampling and time amplifier for all digital phase-locked loopFull-text access may be available. Sign in or learn about subscription options.pp. 285-288
by Kuo-Hsing Cheng, Chang-Chien Hu, Jen-Chieh Liu, Hong-Yi Huang
Notice of Removal: Synthesis of online testable reversible circuitFull-text access may be available. Sign in or learn about subscription options.pp. 277-280
by Dipak K. Kole, Hafizur Rahaman, Debesh K. Das, Bhargab B. Bhattacharya
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A hardware accelerated framework for the generation of design validation programs for SMT processorsFull-text access may be available. Sign in or learn about subscription options.pp. 289-292
by D. Ravotto, E. Sanchez, M. Sonza Reorda
On analysis of fabricated polymorphic circuitsFull-text access may be available. Sign in or learn about subscription options.pp. 281-284
by Vaclav Simek, Richard Ruzicka, Lukas Sekanina
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A 0.4 V bulk-input pseudo amplifier in 90nm CMOS technologyFull-text access may be available. Sign in or learn about subscription options.pp. 301-304
by A. Ahmadpour
Non-disjoint decomposition of logic functions in Reed-Muller spectral domainFull-text access may be available. Sign in or learn about subscription options.pp. 293-296
by Edward Hrynkiewicz, Stefan Kołodziński
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A novel SRAM-based FPGA architecture for defect and fault tolerance of configurable logic blocksFull-text access may be available. Sign in or learn about subscription options.pp. 305-308
by Farid Lahrach, Abderrazek Abdaoui, Abderrahim Doumar, Eric Chatelet
Memory optimizations for packet classification algorithms in FPGAFull-text access may be available. Sign in or learn about subscription options.pp. 297-300
by Viktor Puš, Juraj Blaho, Jan Kořenek
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Synthesizing simulators for model checking microcontroller binary codeFull-text access may be available. Sign in or learn about subscription options.pp. 313-316
by Dominique Guckel, Bastian Schlich, Jorg Brauer, Stefan Kowalewski
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A deterministic approach for hardware fault injection in asynchronous QDI logicFull-text access may be available. Sign in or learn about subscription options.pp. 317-322
by Werner Friesenbichler, Thomas Panhofer, Andreas Steininger
Simulation-based sensitivity and worst-case analyses of automotive electronicsFull-text access may be available. Sign in or learn about subscription options.pp. 309-312
by Monica Rafaila, Christian Decker, Christoph Grimm, Georg Pelz
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Test pattern generation for the combinational representation of asynchronous circuitsFull-text access may be available. Sign in or learn about subscription options.pp. 323-328
by Roland Dobai, Elena Gramatova
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Window optimization of reversible and quantum circuitsFull-text access may be available. Sign in or learn about subscription options.pp. 341-345
by Mathias Soeken, Robert Wille, Gerhard W. Dueck, Rolf Drechsler
Synthesis of asynchronous monitors for critical electronic systemsFull-text access may be available. Sign in or learn about subscription options.pp. 329-334
by Alexandre Porcher, Katell Morin-Allory, Laurent Fesquet
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On logic synthesis of conventionally hard to synthesize circuits using genetic programmingFull-text access may be available. Sign in or learn about subscription options.pp. 346-351
by Petr Fiser, Jan Schmidt, Zdenek Vasicek, Lukas Sekanina
Synthesizing multiplier in reversible logicFull-text access may be available. Sign in or learn about subscription options.pp. 335-340
by Sebastian Offermann, Robert Wille, Gerhard W. Dueck, Rolf Drechsler
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Constraint-based test pattern generation at the Register-Transfer LevelFull-text access may be available. Sign in or learn about subscription options.pp. 352-357
by Taavi Viilukas, Jaan Raik, Maksim Jenihhin, Raimund Ubar, Anna Krivenko
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Comparison of jitter decomposition methods for BER analysis of high-speed serial linksFull-text access may be available. Sign in or learn about subscription options.pp. 370-375
by Stefan Erb, Wolfgang Pribyl
Fault diagnosis of crosstalk induced glitches and delay faultsFull-text access may be available. Sign in or learn about subscription options.pp. 358-363
by Shehzad Hasan, Ajoy K. Palit, Walter Anheier
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Analysis of power consumption and transition fault coverage for LOS and LOC testing schemesFull-text access may be available. Sign in or learn about subscription options.pp. 376-381
by F. Wu, L. Dilillo, A. Bosio, P. Girard, S. Pravossoudovitch, A. Virazel, J. Ma, W. Zhao, M. Tehranipoor, X. Wen
Reduction of power dissipation through parallel optimization of test vector and scan register sequencesFull-text access may be available. Sign in or learn about subscription options.pp. 364-369
by Zdenek Kotasek, Jaroslav Skarvada, Josef Strnadel
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Decoupling capacitance study and optimization method for high-performance VLSIsFull-text access may be available. Sign in or learn about subscription options.pp. 388-392
by Q. K. Zhu, J. Yong, T. Mozdzen
Low-cost, customized and flexible SRAM MBIST engineFull-text access may be available. Sign in or learn about subscription options.pp. 382-387
by Ad van de Goor, Christian Jung, Said Hamdioui, Georgi Gaydadjiev
Versatile sub-bandgap reference IP coreFull-text access may be available. Sign in or learn about subscription options.pp. 393-398
by Tomáš Urban, Ondřej Šubrt, Pravoslav Martinek
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Author indexFreely available from IEEE.pp. 406-407
A 12-bit fully differential 2MS/s successive approximation analog-to-digital converter with reduced power consumptionFull-text access may be available. Sign in or learn about subscription options.pp. 399-402
by M. Davidovic, G. Zach, H. Zimmermann
Receiver synchronization in video streaming with short latency over asynchronous networksFull-text access may be available. Sign in or learn about subscription options.pp. 403-405
by Jiří Halák, Sven Ubik, Petr Žejdl
Cumulative embedded memory failure bitmap display & analysisFull-text access may be available. Sign in or learn about subscription options.pp. 1-6
by N. Campanelli, T. Kerekes, P. Bernardi, M. De Carvalho, A. Panariti, M. Sonza Reorda, D. Appello, M. Barone
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