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Proceedings International Test Conference 1996. Test and Design Validity

Oct. 20 1996 to Oct. 25 1996

Washington, D.C.

ISSN: 1089-3539

ISBN: 0-7803-3543-0

Table of Contents

Proceedings International Test Conference 1996. Test and Design ValidityFreely available from IEEE.pp. 0_2-0_2
Introductory Section
Welcoming MessageFreely available from IEEE.pp. 1
Introductory Section
Steering CommitteeFreely available from IEEE.pp. 2
Introductory Section
Technical Program CommitteeFreely available from IEEE.pp. 4
Introductory Section
Technical Papers Evaluation and Selection ProcessFull-text access may be available. Sign in or learn about subscription options.pp. 7
Introductory Section
1995 Paper AwardsFreely available from IEEE.pp. 8
Introductory Section
ReviewersFreely available from IEEE.pp. 944
Introductory Section
Author IndexFreely available from IEEE.pp. 950
Keynote Address
Emerging Technologies Drive Domain-Specific SolutionsFull-text access may be available. Sign in or learn about subscription options.pp. 10
by Walden (Wally) C. Rhines
Invited Address
New and Not-So-New Test Challenges of the Next DecadeFull-text access may be available. Sign in or learn about subscription options.pp. 11
by Wojciech Maly
Session 2.0: Automatic Test Generation
Test Generation For Ultra-Large Circuits Using ATPG Constraints And Test-Pattern TemplatesFull-text access may be available. Sign in or learn about subscription options.pp. 13
by Peter Wohl, John Waicukauski
Session 2.0: Automatic Test Generation
Test Pattern Generation for Circuits with Asynchronous Signals based on ScanFull-text access may be available. Sign in or learn about subscription options.pp. 21
by Mitsuo Teramoto, Tomoo Fukazawa
Session 2.0: Automatic Test Generation
Accelerated Compact Test Set Generation for Three-State CircuitsFull-text access may be available. Sign in or learn about subscription options.pp. 29
by M. H. Konijnenburg, J. Th. van der Linden, A. J. van de Goor
Comparing topological, symbolic and GA-based ATPGs: an experimental approachFull-text access may be available. Sign in or learn about subscription options.pp. 39-47
by E. Corno, P. Prinetto, M. Rebaudengo, M. Sonza Reorda
Session 3.0: BIST: Architectures And Generators
BIST Fault Diagnosis In Scan-Based VLSI EnvironmentsFull-text access may be available. Sign in or learn about subscription options.pp. 48
by Yuejian Wu, Saman Adham
Session 3.0: BIST: Architectures And Generators
LFSR Reseeding As A Component of Board Level BISTFull-text access may be available. Sign in or learn about subscription options.pp. 58
by Pieter M. Trouborst
Session 3.0: BIST: Architectures And Generators
Using ILA Testing for BIST in FPGAsFull-text access may be available. Sign in or learn about subscription options.pp. 68
by Charles Stroud, Eric Lee, Srinivasa Konala, Miron Abramovici
Session 3.0: BIST: Architectures And Generators
An Effective BIST Scheme for DatapathsFull-text access may be available. Sign in or learn about subscription options.pp. 76
by Dimitris Gizopoulos, Antonis Paschalis, Yervant Zorian
Session 4.0: New Test Considerations For Mixed-Signal Devices
Four Multi Probing Test For 16 Bit DAC With Vertical Contact Probe CardFull-text access may be available. Sign in or learn about subscription options.pp. 86
by Seiji Sasho, Teruhisa Sakata
Session 4.0: New Test Considerations For Mixed-Signal Devices
A Demonstration IC For The P1149.4 Mixed Signal Test StandardFull-text access may be available. Sign in or learn about subscription options.pp. 92
by Keith Lofstrom
Session 4.0: New Test Considerations For Mixed-Signal Devices
Testing The Digital Modulation of PHS DevicesFull-text access may be available. Sign in or learn about subscription options.pp. 99
by Koji Asami
Session 5.0: Topics In Test Hardware
Testing And Characterizing Jitter In 100Base-TX And 155.52 MBit/S ATM Devices With A 1 GSample/S AWG In An ATE SystemFull-text access may be available. Sign in or learn about subscription options.pp. 104
by Barry D. Kulp
A BIST methodology for comprehensive testing of ram with reduced heat dissipationFull-text access may be available. Sign in or learn about subscription options.pp. 386,387,388,389,390,391,392,393,394,395,396,397,398,399,400
by H. Cheung, S.K. Gupta
Session 5.0: Topics In Test Hardware
High-Speed IDDQ Measurement CircuitFull-text access may be available. Sign in or learn about subscription options.pp. 112
by Kenji Isawa, Yoshihiro Hashimoto
Session 5.0: Topics In Test Hardware
Extending Calibration IntervalsFull-text access may be available. Sign in or learn about subscription options.pp. 118
by Solomon Max
Session 5.0: Topics In Test Hardware
Manufacturing Test of Fibre Channel Communications Cards And Optical SubassembliesFull-text access may be available. Sign in or learn about subscription options.pp. 127
by Steven DeFoster, Dennis Karst, Matthew Peterson, Paul Sendelbach, Kirk Kottschade
Session 6.0: Practical And Higher-Level Fault Simulation
A Universal Technique for Accelerating Simulation of Scan Test PatternsFull-text access may be available. Sign in or learn about subscription options.pp. 135
by Bejoy G. Oomman, Wu-Tung Cheng, John Waicukauski
Session 6.0: Practical And Higher-Level Fault Simulation
On Potential Fault Detection in Sequential CircuitsFull-text access may be available. Sign in or learn about subscription options.pp. 142
by Elizabeth M. Rudnick, Janak H. Patel, Irith Pomeranz
Session 6.0: Practical And Higher-Level Fault Simulation
Improving Gate Level Fault Coverage by RTL Fault GradingFull-text access may be available. Sign in or learn about subscription options.pp. 150
by Weiwei Mao, Ravi K. Gulati
Session 6.0: Practical And Higher-Level Fault Simulation
Distributed Mixed Level Logic And Fault Simulation On The Pentium?Pro MicroprocessorFull-text access may be available. Sign in or learn about subscription options.pp. 160
by Sankaran Karthik, Mark Aitken, Glidden Martin, Srinivasu Pappula, Bob Stettler, Praveen Vishakantaiah, Manuel d?Abreu, Jacob A. Abraham
Session 7.0: BIST Pattern Generation
Altering A Pseudo-Random Bit Sequence For Scan-Based BISTFull-text access may be available. Sign in or learn about subscription options.pp. 167
by Nur A. Touba, Edward J. McCluskey
Session 7.0: BIST Pattern Generation
MFBIST: A BIST Method For Random Pattern Resistant CircuitsFull-text access may be available. Sign in or learn about subscription options.pp. 176
by Mohammed F. AlShaibi, Charles R. Kime
Session 7.0: BIST Pattern Generation
Two-Dimensional Test Data Decompressor for Multiple Scan DesignsFull-text access may be available. Sign in or learn about subscription options.pp. 186
by N. Zacharia, J. Rajski, J. Tyszer, J. A. Waicukauski
Session 7.0: BIST Pattern Generation
Mixed-Mode BIST Using Embedded ProcessorsFull-text access may be available. Sign in or learn about subscription options.pp. 195
by Sybille Hellebrand, Hans-Joachim Wunderlich, Andre Hertwig
Session 8.0: Testing of Asynchronous Circuits
Test Quality of Asynchronous Circuits: A Defect-oriented EvaluationFull-text access may be available. Sign in or learn about subscription options.pp. 205
by Marly Roncken, Eric Bruls
Session 8.0: Testing of Asynchronous Circuits
Optimal Scan for Pipelined Testing: An Asynchronous FoundationFull-text access may be available. Sign in or learn about subscription options.pp. 215
by Marly Roncken, Emile Aarts, Wim Verhaegh
Session 8.0: Testing of Asynchronous Circuits
An Asynchronous Scan Path Concept for Micropipelines using the Bundled Data ConventionFull-text access may be available. Sign in or learn about subscription options.pp. 225
by Volker Sch?ber, Thomas Kiel
Session 8.0: Testing of Asynchronous Circuits
Synthesis-for-Initializability of Asynchronous Sequential MachinesFull-text access may be available. Sign in or learn about subscription options.pp. 232
by Montek Singh, Steven M. Nowick
Session 9.0: Industry Impact: Screening, Test, And Measurement Breakthroughs
Burn-in Elimination of a High Volume Microprocessor Using IDDQFull-text access may be available. Sign in or learn about subscription options.pp. 242
by Timothy R. Henry, Thomas Soo
Session 9.0: Industry Impact: Screening, Test, And Measurement Breakthroughs
IDDQ And AC Scan: The War Against Unmodelled DefectsFull-text access may be available. Sign in or learn about subscription options.pp. 250
by Peter C. Maxwell, Robert C. Aitken, Kathleen R. Kollitz, Allen C. Brown
Session 9.0: Industry Impact: Screening, Test, And Measurement Breakthroughs
High Resolution IDDQ Characterization and Testing - Practical IssuesFull-text access may be available. Sign in or learn about subscription options.pp. 259
by Alan W. Righter, Jerry M. Soden, Richard W. Beegle
Session 9.0: Industry Impact: Screening, Test, And Measurement Breakthroughs
Novel Optical Probing System With Submicron Spatial Resolution For Internal Diagnosis of VLSI CircuitsFull-text access may be available. Sign in or learn about subscription options.pp. 269
by K. Ozaki, H. Sekiguchi, S. Wakana, Y. Goto, Y. Umehara, J. Matsumoto
Session 10.0: Fault Simulation And Diagnosis of Delay Faults
An Exact Non-Enumerative Fault Simulator For Path-Delay FaultsFull-text access may be available. Sign in or learn about subscription options.pp. 276
by Marwan A. Gharaybeh, Michael L. Bushnell, Vishwani D. Agrawal
Session 10.0: Fault Simulation And Diagnosis of Delay Faults
A Diagnostic ATPG for Delay Faults Based on Genetic AlgorithmsFull-text access may be available. Sign in or learn about subscription options.pp. 286
by P. Girard, C. Landrault, S. Pravossoudovitch, B. Rodriguez
Session 10.0: Fault Simulation And Diagnosis of Delay Faults
Dignostic Fault Equivalence Identification Using Redundancy Information & Structural AnalysisFull-text access may be available. Sign in or learn about subscription options.pp. 294
by Ismed Hartanto, Vamsi Boppana, W. Kent Fuchs
Session 11.0: Memory Test: Design For Testability
Self-Learning Signature Analysis for Non-Volatile Memory TestingFull-text access may be available. Sign in or learn about subscription options.pp. 303
by Piero Olivo, Marcello Dalpasso
Session 11.0: Memory Test: Design For Testability
Weak Write Test Mode: an SRAM Cell Stability Design for Test TechniqueFull-text access may be available. Sign in or learn about subscription options.pp. 309
by Anne Meixner, Jash Banik
Session 11.0: Memory Test: Design For Testability
A Built-In Self-Test Circuit with Timing Margin Test Function in a 1Gbit Synchronous DRAMFull-text access may be available. Sign in or learn about subscription options.pp. 319
by Narumi Sakashita, Fumihiro Okuda, Ken'ichi Shimomura, Hiroki Shimano, Mitsuhiro Hamada, Tetsuo Tada, Shinji Komori, Kazuo Kyuma, Akihiko Yasuoka, Haruhiko Abe
Session 12.0: Board Test Challenges And Solutions
Analog/Digital Testing of Loaded Boards Without Dedicated Test PointsFull-text access may be available. Sign in or learn about subscription options.pp. 325
by Christophe Vaucher, Louis Balme
Session 12.0: Board Test Challenges And Solutions
Opens Board Test Coverage: When Is 99% Really 40%?Full-text access may be available. Sign in or learn about subscription options.pp. 333
by Mick M. V. Tegethoff, Kenneth P. Parker, Ken Lee
Session 12.0: Board Test Challenges And Solutions
A Roadmap for Boundary-Scan Test ReuseFull-text access may be available. Sign in or learn about subscription options.pp. 340
by Gene Wedge, Tom Conner
Session 13.0: Delay-Fault Testing I
Local Transformations and Robust Dependent Path Delay FaultsFull-text access may be available. Sign in or learn about subscription options.pp. 347
by Harry Hengster, Uwe Sparmann, Bernd Becker, Sudhakar M. Reddy
Session 13.0: Delay-Fault Testing I
On Cancelling the Effects of Logic Sharing for Improved Path Delay Fault TestabilityFull-text access may be available. Sign in or learn about subscription options.pp. 357
by Irith Pomeranz, Sudhakar M. Reddy
Session 13.0: Delay-Fault Testing I
Detecting Delay Flaws by Very-Low-Voltage TestingFull-text access may be available. Sign in or learn about subscription options.pp. 367
by Jonathan T.-Y. Chang, Edward J. McCluskey
Session 14.0: Microprocessor Test
Testability Features for a Submicron Voice-coder ASICFull-text access may be available. Sign in or learn about subscription options.pp. 377
by F. Pichon
Session 14.0: Microprocessor Test
A BIST Methodology For Comprehensive Testing of RAM With Reduced Head DissipationFull-text access may be available. Sign in or learn about subscription options.pp. 386
by Hugo Cheung, Sandeep K. Gupta
Session 14.0: Microprocessor Test
DFT Strategy For Intel MicroprocessorsFull-text access may be available. Sign in or learn about subscription options.pp. 396
by Wayne Needham, Naga Gollakota
Session 15.0: An Evolving Mixed-Signal Boundary-Scan Standard
Proposal To Simplify Development Of A Mixed Signal Test StandardFull-text access may be available. Sign in or learn about subscription options.pp. 400
by Lee Whetsel
Session 15.0: An Evolving Mixed-Signal Boundary-Scan Standard
A Method of Extending an 1149.1 Bus for Mixed-Signal TestingFull-text access may be available. Sign in or learn about subscription options.pp. 410
by Robert J. Russell
Session 15.0: An Evolving Mixed-Signal Boundary-Scan Standard
Early Capture For Boundary Scan Timing MeasurementsFull-text access may be available. Sign in or learn about subscription options.pp. 417
by Keith Lofstrom
Session 16.0: Delay Fault Testing II
Identification and Test Generation for Primitive FaultsFull-text access may be available. Sign in or learn about subscription options.pp. 423
by Angela Krstic, Kwang-Ting (Tim) Cheng, Srimat T. Chakradhar
Session 16.0: Delay Fault Testing II
Test Generation For Global Delay FaultsFull-text access may be available. Sign in or learn about subscription options.pp. 433
by G. M. Luong, D. M. H. Walker
Session 16.0: Delay Fault Testing II
ATPD: An Automatic Test Pattern Generator For Path Delay FaultsFull-text access may be available. Sign in or learn about subscription options.pp. 443
by D. Karayiannis, S. Tragoudas
Session 17.0: Software For New Test Strategies
Scan Design Oriented Test Technique For VLSI's Using ATEFull-text access may be available. Sign in or learn about subscription options.pp. 453
by Yasuji Oyama, Toshinobu Kanai, Hironobu Niijima
Session 17.0: Software For New Test Strategies
Virtual Test of Noise And Jitter ParametersFull-text access may be available. Sign in or learn about subscription options.pp. 461
by K. Helmreich, G. Reinwardt
Session 17.0: Software For New Test Strategies
A Novel Approach to the Analysis of VLSI Device Test ProgramsFull-text access may be available. Sign in or learn about subscription options.pp. 471
by Yuhai Ma, Wanchun Shi
Session 18.0: Innovations In Current Testing
Digital Integrated Circuit Testing using Transient Signal AnalysisFull-text access may be available. Sign in or learn about subscription options.pp. 481
by James F. Plusquellic, Donald M. Chiarulli, Steven P. Levitan
Session 18.0: Innovations In Current Testing
Towards an Effective IDDQ Test Vector Selection and Application MethodologyFull-text access may be available. Sign in or learn about subscription options.pp. 491
by Jos van Sas, Urbain Swerts, Marc Darquennes
Session 18.0: Innovations In Current Testing
Correlating Defects To Functional And IDDQ TestsFull-text access may be available. Sign in or learn about subscription options.pp. 501
by Theo J. Powell, James R. Pair, Bernard G. Carbajal III
Session 19.0: Mixed-Signal DFT And Fault Simulation
Defect-Oriented vs Schematic-Level Based Fault Simulation For Mixed-Signal ICsFull-text access may be available. Sign in or learn about subscription options.pp. 511
by Thomas Olbrich, Jordi P?rez, Ian A. Grout, Andrew M. D. Richardson, Carles Ferrer
Session 19.0: Mixed-Signal DFT And Fault Simulation
Hierarchy based Statistical Fault Simulation of Mixed-Signal ICsFull-text access may be available. Sign in or learn about subscription options.pp. 521
by Giri Devarayanadurg, Prashant Goteti, Mani Soma
Session 19.0: Mixed-Signal DFT And Fault Simulation
An Integration of Memory-Based Analog Signal Generation Into Current DFT ArchitecturesFull-text access may be available. Sign in or learn about subscription options.pp. 528
by Evan M. Hawrysh, Gordon W. Roberts
Session 20.0: DFT: Inching Forward With Partial-Scan Design
Partial Scan Design Based on State Transition ModelingFull-text access may be available. Sign in or learn about subscription options.pp. 538
by Vamsi Boppana, W. Kent Fuchs
Session 20.0: DFT: Inching Forward With Partial-Scan Design
A Global Algorithm for the Partial Scan Design Problem Using Circuit State InformationFull-text access may be available. Sign in or learn about subscription options.pp. 548
by Dong Xiang, Janak H. Patel
Partial scan flip flop selection for simulation-based sequential ATPGsFull-text access may be available. Sign in or learn about subscription options.pp. 558-564
by F. Corno, P. Prinetto, M. Rebaudengo, M. Sonza Reorda
Session 21.0: Test Languages And Tools
Standard Test Interface Language (STIL) A New Language for Patterns and WaveformsFull-text access may be available. Sign in or learn about subscription options.pp. 565
by Tony Taylor, Gregory A. Maston
Two new techniques for identifying opens on printed circuit boards: analog, junction test, and radio frequency induction testFull-text access may be available. Sign in or learn about subscription options.pp. 927
by J. Wrinn
Session 21.0: Test Languages And Tools
LIMSoft: Automated Tool for Design and Test Integration of Analog CircuitsFull-text access may be available. Sign in or learn about subscription options.pp. 571
by Naim Ben Hamida, Khaled Saab, David Marche, Bozena Kaminska, Guy Quesnel
Session 21.0: Test Languages And Tools
Developing A Testing Maturity Model For Software Test Process Evaluation And ImprovementFull-text access may be available. Sign in or learn about subscription options.pp. 581
by Ilene Burnstein, Taratip Suwanassart, Robert Carlson
Session 22.0: Application of SPC to IC Design, Manufacturing And Test
ASIC Yield Estimation At Early Design CycleFull-text access may be available. Sign in or learn about subscription options.pp. 590
by Vonkyoung Kim, Mick Tegethoff, Tom Chen
Session 22.0: Application of SPC to IC Design, Manufacturing And Test
Risk Assessment Sampling Plans for Non-Standard (Maverick) MaterialFull-text access may be available. Sign in or learn about subscription options.pp. 595
by Daniel P. Core
Session 22.0: Application of SPC to IC Design, Manufacturing And Test
SPC On The IC-Production Test ProcessFull-text access may be available. Sign in or learn about subscription options.pp. 605
by Jos van der Peet, Ger van Boxem
Session 23.0: New Techniques For Realistic Faults
Beyond the Byzantine Generals: Unexpected Behavior and Bridging Fault DiagnosisFull-text access may be available. Sign in or learn about subscription options.pp. 611
by David B. Lavo, Tracy Larrabee, Brian Chess
Session 23.0: New Techniques For Realistic Faults
Defect-Oriented IC Test and Diagnosis Using VHDL Fault SimulationFull-text access may be available. Sign in or learn about subscription options.pp. 620
by F. Celeiro, L. Dias, J. Ferreira, M. B. Santos, J. P. Teixeira
Session 23.0: New Techniques For Realistic Faults
Using Target Faults To Detect Non-Target DefectsFull-text access may be available. Sign in or learn about subscription options.pp. 629
by Li-C Wang, Thomas W. Williams, M. Ray Mercer
Session 24: Design-For-Testability Inspirations
A Unifying Methodology For Intellectual Property And Custom Logic TestingFull-text access may be available. Sign in or learn about subscription options.pp. 639
by Sandeep Bhatia, Tushar Gheewala, Prab Varma
Session 24: Design-For-Testability Inspirations
Constructive Multi-Phase Test Point Insertion for Scan-Based BISTFull-text access may be available. Sign in or learn about subscription options.pp. 649
by Nagesh Tamarapalli, Janusz Rajski
Session 24: Design-For-Testability Inspirations
Ortohgonal Scan: Low Overhead Scan For Data PathsFull-text access may be available. Sign in or learn about subscription options.pp. 659
by Robert B. Norwood, Edward J. McCluskey
Session 25.0: High Frequency And Timing In ATE
An Application of Photoconductive Switch For High-Speed TestingFull-text access may be available. Sign in or learn about subscription options.pp. 669
by Kazunori Chihara, Takashi Sekino, Koji Sasaki
Session 25.0: High Frequency And Timing In ATE
Generation Technique of 500MHz Ultra-High Speed Algorithmic PatternFull-text access may be available. Sign in or learn about subscription options.pp. 677
by Hideaki Imada, Kenichi Fujisaki, Toshimi Ohsawa, Masaru Tsuto
Session 25.0: High Frequency And Timing In ATE
The Effect of Period Generation Techniques on Period Resolution and Waveform Jitter in VLSI Test SystemsFull-text access may be available. Sign in or learn about subscription options.pp. 685
by Michael G. Davis
Session 26.0: Topics In Test Engineering
Analysis And Detection of Timing Failures In An Experimental Test ChipFull-text access may be available. Sign in or learn about subscription options.pp. 691
by Piero Franco, Siyad Ma, Jonathan Chang, Yi-Chin Chu, Sanjay Wattal, E. J. McCluskey, Robert L. Stokes, William D. Farwell
Session 26.0: Topics In Test Engineering
A Unique Methodology for At-Speed Test of cDSP(TM) and ASIC DevicesFull-text access may be available. Sign in or learn about subscription options.pp. 701
by David Potts, Roger Griesmer
Session 26.0: Topics In Test Engineering
Cost Effective Frequency Measurement for Production TestingFull-text access may be available. Sign in or learn about subscription options.pp. 708
by Ralf Stoffels
Session 27.0: System Test: Practical Aspects, Partitioning And Simulation
Backplane Interconnect Test In A Boundary-Scan EnvironmentFull-text access may be available. Sign in or learn about subscription options.pp. 717
by Wuudiann Ke
Session 27.0: System Test: Practical Aspects, Partitioning And Simulation
Testability-Oriented Hardware/Software PartitioningFull-text access may be available. Sign in or learn about subscription options.pp. 725
by Yves Le Traon, Ghassan Al Hayek, Chantal Robach
Session 27.0: System Test: Practical Aspects, Partitioning And Simulation
System Level Fault SimulationFull-text access may be available. Sign in or learn about subscription options.pp. 732
by Pablo S?nchez, Isabel Hidalgo
Session 28.0: Test Synthesis Solutions
ASIC BIST Synthesis: A VHDL ApproachFull-text access may be available. Sign in or learn about subscription options.pp. 741
by Tom Eberle, Bob McVay, Chris Meyers, Jason Moore
Session 28.0: Test Synthesis Solutions
Integrating Scan Into Hierarchical Synthesis MethodologiesFull-text access may be available. Sign in or learn about subscription options.pp. 751
by James Beausang, Chris Ellingham, Markus Robinson
Session 28.0: Test Synthesis Solutions
Synthesis Of Self-Testing Finite State Machines From High-Level SpecificationFull-text access may be available. Sign in or learn about subscription options.pp. 757
by Vishwani D. Agrawal, R. D. (Shawn) Blanton, Maurizio Damiani
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