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1990 International Test Conference

Sept. 10 1990 to Sept. 14 1990

Washington, DC, USA

Table of Contents

Proceedings International Test Conference 1990 (Cat. No.90CH2910-6)Freely available from IEEE.pp. 0_1-0_1
Challenge of design and test of ultra-large-scale circuitsFull-text access may be available. Sign in or learn about subscription options.pp. 23-23
by A. Yamada
A method to calculate necessary assignments in algorithmic test pattern generationFull-text access may be available. Sign in or learn about subscription options.pp. 25,26,27,28,29,30,31,32,33,34
by J. Rajski, H. Cox
Global cost functions for test generationFull-text access may be available. Sign in or learn about subscription options.pp. 35,36,37,38,39,40,41,42,43
by M. Abramovici, D.T. Miller, R. Henning
ATPG for ultra-large structured designsFull-text access may be available. Sign in or learn about subscription options.pp. 44,45,46,47,48,49,50,51
by J.A. Waicukauski, P.A. Shupe, D.J. Giramma, A. Matin
A diagnostic test pattern generation algorithmFull-text access may be available. Sign in or learn about subscription options.pp. 52-58
by P. Camurati, D. Medina, P. Prinetto, M. Sonza Reorda
Analog test requirements of linear echo cancellation ISDN devicesFull-text access may be available. Sign in or learn about subscription options.pp. 59,60,61,62,63,64,65,66,67
by D.K. Oka
Test features of the MC145472 ISDN U-transceiversFull-text access may be available. Sign in or learn about subscription options.pp. 68,69,70,71,72,73,74,75,76,77,78,79
by L. Bonet, J. Ganger, J. Girardeau, C. Greaves, M. Pendleton, D. Yatim
Fast and accurate testing of ISDN S/T interface devices using pseudo error rate techniquesFull-text access may be available. Sign in or learn about subscription options.pp. 80,81,82,83,84,85
by B.W. Sprinkle
ATE-based functional ISDN testingFull-text access may be available. Sign in or learn about subscription options.pp. 86,87,88,89,90,91,92,93,94
by K. Lanier
ASSIST (Allied Signal's Standardized Integrated Scan Test)Full-text access may be available. Sign in or learn about subscription options.pp. 95,96,97,98,99,100,101,102
by G. Sapp
Innovative techniques for improved testabilityFull-text access may be available. Sign in or learn about subscription options.pp. 103,104,105,106,107,108
by E.F. Sarkany, R.F. Lusch
Testability implemented in the VAX 6000 model 400Full-text access may be available. Sign in or learn about subscription options.pp. 109,110,111,112,113,114
by J. Sweeney
Scan based guided probe technology delivers Cyclone to the marketFull-text access may be available. Sign in or learn about subscription options.pp. 115,116,117,118,119
by C.J. Choi
Optimal placement of IEEE 1149.1 test port and boundary scan resources for wafer scale integrationFull-text access may be available. Sign in or learn about subscription options.pp. 120,121,122,123,124,125,126
by D.L. Landis, P. Singh
Hierarchical self-test concept based on the JTAG standardFull-text access may be available. Sign in or learn about subscription options.pp. 127,128,129,130,131,132,133,134
by J. Maierhofer
Event qualification: a gateway to at-speed system testingFull-text access may be available. Sign in or learn about subscription options.pp. 135,136,137,138,139,140,141
by L. Whetsel
Mixed-mode ATPG under input constraintsFull-text access may be available. Sign in or learn about subscription options.pp. 142,143,144,145,146,147,148,149,150,151
by C.T. Glover
Multiple path sensitization for hierarchical circuit testingFull-text access may be available. Sign in or learn about subscription options.pp. 152,153,154,155,156,157,158,159,160,161
by Chau-Chin Su, C.R. Kime
Functional test generation for finite state machinesFull-text access may be available. Sign in or learn about subscription options.pp. 162,163,164,165,166,167,168
by K.-T. Cheng, J.-Y. Jou
A comprehensive approach for modeling and testing analog and mixed-signal devicesFull-text access may be available. Sign in or learn about subscription options.pp. 169,170,171,172,173,174,175,176
by T.M. Souders, G.N. Stenbakken
From specification to measurement: the bottleneck in analog industrial testingFull-text access may be available. Sign in or learn about subscription options.pp. 177,178,179,180,181,182
by R.J. van Rijsinge, A.A.R.M. Haggenburg, C. de Vries, H. Wallinga
A design-for-test methodology for active analog filtersFull-text access may be available. Sign in or learn about subscription options.pp. 183,184,185,186,187,188,189,190,191,192
by M. Soma
Stress profile derivation-an empirical approachFull-text access may be available. Sign in or learn about subscription options.pp. 193,194,195,196,197,198,199,200,201,202,203,204,205,206,207
by A.C. Walker
Automatic electro-optical testing of automobile dashboard displays in a factory environmentFull-text access may be available. Sign in or learn about subscription options.pp. 208,209,210,211,212,213
by F.J. Langley, C.A. Robinson, R.A. Passero
Time margin issues in disk drive testingFull-text access may be available. Sign in or learn about subscription options.pp. 214,215,216,217,218,219,220,221
by D. Gill
A language for describing boundary-scan devicesFull-text access may be available. Sign in or learn about subscription options.pp. 222,223,224,225,226,227,228,229,230,231,232,233,234
by K.P. Parker, S. Oresjo
Boundary scan test used at board level: moving towards realityFull-text access may be available. Sign in or learn about subscription options.pp. 235,236,237,238,239,240,241,242
by F. de Jong
ATPG issues for board designs implementing boundary scanFull-text access may be available. Sign in or learn about subscription options.pp. 243,244,245,246,247,248,249,250,251
by D. Sterba, A. Halliday, D. McClean
Why, I/sub DDQ/? (CMOS IC testing)Full-text access may be available. Sign in or learn about subscription options.pp. 252
by S. McEuen
I/sub DDQ/ testing because 'zero defects isn't enough': a Philips perspectiveFull-text access may be available. Sign in or learn about subscription options.pp. 253,254
by K. Baker, B. Verhelst
Zero defects or zero stuck-at faults-CMOS IC process improvement with I/sub DDQ/Full-text access may be available. Sign in or learn about subscription options.pp. 255,256
by J.M. Soden, R.R. Fritzemeier, C.F. Hawkins
Current testingFull-text access may be available. Sign in or learn about subscription options.pp. 257
by W. Maly
Concurrent engineeringFull-text access may be available. Sign in or learn about subscription options.pp. 258,259
by A. Lowenstein, S. Schlosser, G. Winter
Obstacles and an approach towards concurrent engineeringFull-text access may be available. Sign in or learn about subscription options.pp. 260,261
by M.A. Breuer
QML (qualified manufacturing line): a method of providing high quality integrated circuitsFull-text access may be available. Sign in or learn about subscription options.pp. 262,263
by N.E. Donlin
Test engineers role in QMLFull-text access may be available. Sign in or learn about subscription options.pp. 264
by R.W. Thomas
Testability preserving transformations in multi-level logic synthesisFull-text access may be available. Sign in or learn about subscription options.pp. 265,266,267,268,269,270,271,272,273
by J. Rajski, J. Vasudevamurthy
Sequential logic synthesis for testability using register-transfer level descriptionsFull-text access may be available. Sign in or learn about subscription options.pp. 274,275,276,277,278,279,280,281,282,283
by A. Ghosh, S. Davadas, A.R. Newton
Design of integrated circuits fully testable for delay-faults and multifaultsFull-text access may be available. Sign in or learn about subscription options.pp. 284,285,286,287,288,289,290,291,292,293
by S. Devadas, K. Keutzer
Functional test and diagnosis: a proposed JTAG sample mode scan testerFull-text access may be available. Sign in or learn about subscription options.pp. 294,295,296,297,298,299,300,301,302,303
by M.E. Lefebvre
Scan test architectures for digital board testersFull-text access may be available. Sign in or learn about subscription options.pp. 304,305,306,307,308,309,310
by M.L. Fichtenbaum, G.D. Robinson
The boundary-scan master: target applications and functional requirementsFull-text access may be available. Sign in or learn about subscription options.pp. 311,312,313,314,315
by C.W. Yau, N. Jarwala
Efficient UBIST implementation for microprocessor sequencing partsFull-text access may be available. Sign in or learn about subscription options.pp. 316,317,318,319,320,321,322,323,324,325,326
by M. Nicolaidis
Realization of an efficient design verification test used on a microinstruction controlled self testFull-text access may be available. Sign in or learn about subscription options.pp. 327,328,329,330,331,332,333,334,335,336
by Y. Nozuyama
Testability considerations in the design of the MC68340 Integrated Processor UnitFull-text access may be available. Sign in or learn about subscription options.pp. 337,338,339,340,341,342,343,344,345,346
by P.E. Bishop, G.L. Giles, S.N. Iyengar, C.T. Glover, W.-o. Law
A high-speed pin-memory architecture using multiport dynamic RAMsFull-text access may be available. Sign in or learn about subscription options.pp. 347,348,349,350,351,352,353,354
by S.-J. Tsai, W.-J. Lee
Sequencer Per Pin test system architectureFull-text access may be available. Sign in or learn about subscription options.pp. 355,356,357,358,359,360,361
by B. West, T. Napier
Multiplexing test system channels for data rates above 1 Gb/sFull-text access may be available. Sign in or learn about subscription options.pp. 362,363,364,365,366,367,368
by D.C. Keezer
Design of scan-testable CMOS sequential circuitsFull-text access may be available. Sign in or learn about subscription options.pp. 369,370,371,372,373,374,375,376
by B.-H. Park, P.R. Menon
An optimization based approach to the partial scan design problemFull-text access may be available. Sign in or learn about subscription options.pp. 377,378,379,380,381,382,383,384,385,386
by V. Chickermane, J.H. Patel
Arrangement of latches in scan-path design to improve delay fault coverageFull-text access may be available. Sign in or learn about subscription options.pp. 387,388,389,390,391,392,393
by W. Mao, M.D. Ciletti
An interactive environment for the transparent logic simulation and testing of integrated circuitsFull-text access may be available. Sign in or learn about subscription options.pp. 394,395,396,397,398,399,400,401,402,403
by G.L. Castrodale, A. Dollas, W.T. Krakow
ASIC CAD system based on hierarchical design-for-testabilityFull-text access may be available. Sign in or learn about subscription options.pp. 404,405,406,407,408,409
by M. Emori, T. Aikyo, Y. Machida, J.-i. Shikatani
CMP3F: a high speed fault simulator for the Connection MachineFull-text access may be available. Sign in or learn about subscription options.pp. 410,411,412,413,414,415,416
by A. Agrawal, D. Bhattacharya
On the charge sharing problem in CMOS stuck-open fault testingFull-text access may be available. Sign in or learn about subscription options.pp. 417,418,419,420,421,422,423,424,425,426
by K.-J. Lee, M.A. Breuer
Increased CMOS IC stuck-at fault coverage with reduced I/sub DDQ/ test setsFull-text access may be available. Sign in or learn about subscription options.pp. 427,428,429,430,431,432,433,434,435
by R.R. Fritzemeier, J.M. Soden, R.K. Treece, C.F. Hawkins
Testing for parametric faults in static CMOS circuitsFull-text access may be available. Sign in or learn about subscription options.pp. 436,437,438,439,440,441,442,443
by F.J. Ferguson, M. Taylor, T. Larrabee
Frequency enhancement of digital VLSI test systemsFull-text access may be available. Sign in or learn about subscription options.pp. 444,445,446,447,448,449,450,451
by L. Ackner, M.R. Barber
Criteria for analyzing high frequency testing performance of VLSI automatic test equipmentFull-text access may be available. Sign in or learn about subscription options.pp. 452,453,454,455,456,457,458,459,460,461
by P. Burlison
Critical parameters for high-performance dynamic response measurementsFull-text access may be available. Sign in or learn about subscription options.pp. 462,463,464,465,466,467,468,469,470,471
by D.F. Murray, C.M. Nash
Integrating boundary scan test into an ASIC design flowFull-text access may be available. Sign in or learn about subscription options.pp. 472,473,474,475,476,477
by M. Muris
A study of the optimization of DC parametric testsFull-text access may be available. Sign in or learn about subscription options.pp. 478,479,480,481,482,483,484,485,486,487
by J.M. Chang
Direct access test scheme-design of block and core cells for embedded ASICsFull-text access may be available. Sign in or learn about subscription options.pp. 488,489,490,491,492
by V. Immaneni, S. Raman
Color reproduction test for CCD image sensorsFull-text access may be available. Sign in or learn about subscription options.pp. 493,494,495,496,497
by H. Kato
A rapid dither algorithm advances A/D converter testingFull-text access may be available. Sign in or learn about subscription options.pp. 498,499,500,501,502,503,504,505,506,507
by J. Weimer, K. Baade, J. Fitzsimmons, B. Lowe
An advanced test system architecture for synchronous and asynchronous control of mixed signal device testingFull-text access may be available. Sign in or learn about subscription options.pp. 508,509,510,511,512,513
by J. Kurita, N. Kasuga, K. Hiwada
An analysis of ATE computational architectureFull-text access may be available. Sign in or learn about subscription options.pp. 514,515,516,517,518,519
by A.R. Taylor
Hierarchical test assembly for macro based VLSI designFull-text access may be available. Sign in or learn about subscription options.pp. 520,521,522,523,524,525,526,527,528,529
by J. Leenstra, L. Spaanenburg
enVision: the inside storyFull-text access may be available. Sign in or learn about subscription options.pp. 530,531,532,533,534,535,536
by D. Organ
State transition graph analysis as a key to BIST fault coverageFull-text access may be available. Sign in or learn about subscription options.pp. 537,538,539,540,541,542,543
by O. Brynestad, E.J. Aas, A.E. Vallestad
Error masking in self-testable circuitsFull-text access may be available. Sign in or learn about subscription options.pp. 544,545,546,547,548,549,550,551,552
by A.P. Stroele, H.-J. Wunderlich
A study of faulty signatures using a matrix formulationFull-text access may be available. Sign in or learn about subscription options.pp. 553,554,555,556,557,558,559,560,561
by J.C. Chan, J.A. Abraham
An architecture for high-speed analog in-circuit testingFull-text access may be available. Sign in or learn about subscription options.pp. 562,563,564
by L. Klein, J. Bridgeman
Diagnosis for wiring interconnectsFull-text access may be available. Sign in or learn about subscription options.pp. 565,566,567,568,569,570,571
by W.-T. Cheng, J.L. Lewandowski, E. Wu
Interconnect testing of boards with partial boundary scanFull-text access may be available. Sign in or learn about subscription options.pp. 572,573,574,575,576,577,578,579,580,581
by G.D. Robinson, J.G. Deshayes
Towards a standard approach for controlling board-level test functionsFull-text access may be available. Sign in or learn about subscription options.pp. 582,583,584,585,586,587,588,589,590
by B.I. Dervisoglu
A new approach to mixed-signal diagnosisFull-text access may be available. Sign in or learn about subscription options.pp. 591,592,593,594,595,596,597
by R. Rastogi, K. Sierzega
Fast embedded A/D converter testing using the microcontroller's resourcesFull-text access may be available. Sign in or learn about subscription options.pp. 598,599,600,601,602,603,604
by R. Bobba, B. Stevens
A fourth generation analog incircuit program generatorFull-text access may be available. Sign in or learn about subscription options.pp. 605,606,607,608,609,610,611,612
by D.T. Crook
Jitter minimization technique for mixed signal testingFull-text access may be available. Sign in or learn about subscription options.pp. 613,614,615,616,617,618,619
by Y. Furukawa, M. Kimura, M. Sugai, S. Kimura, M. Purtell
Networking verification process and environments: an extension of the product realization process for new network capabilitiesFull-text access may be available. Sign in or learn about subscription options.pp. 620,621,622,623,624,625,626
by Y.M. Mastoris, P.D. Nash
Optimized testing of meshesFull-text access may be available. Sign in or learn about subscription options.pp. 627,628,629,630,631,632,633,634,635,636,637
by M. Malek, B. Ozden
Identification of faulty processing elements by space-time compression of test responsesFull-text access may be available. Sign in or learn about subscription options.pp. 638,639,640,641,642,643,644,645,646,647
by M.G. Karpovsky, L.B. Levitin, F.S. Vainstein
Failure probability algorithm for test systems to reduce false alarmsFull-text access may be available. Sign in or learn about subscription options.pp. 648,649,650,651,652,653,654,655,656
by D.R. Allen
A multiple seed linear feedback shift registerFull-text access may be available. Sign in or learn about subscription options.pp. 657,658,659
by J. Savir, W.H. McAnney
A new procedure for weighted random built-in self-testFull-text access may be available. Sign in or learn about subscription options.pp. 660,661,662,663,664,665,666,667,668,669
by F. Muradali, V.K. Agarwal, B. Nadeau-Dostie
Generating pseudo-exhaustive vectors for external testingFull-text access may be available. Sign in or learn about subscription options.pp. 670,671,672,673,674,675,676,677,678,679
by S. Hellebrand, H.-J. Wunderlich, O.F. Haberl
Computer-aided design of pseudoexhaustive BIST for semiregular circuitsFull-text access may be available. Sign in or learn about subscription options.pp. 680,681,682,683,684,685,686,687,688,689
by Chau-Chin Su, C.R. Kime
Fault simulation of logic designs on parallel processors with distributed memoryFull-text access may be available. Sign in or learn about subscription options.pp. 690,691,692,693,694,695,696,697
by L.M. Huisman, R. Daoud
Experimental evaluation of concurrent fault simulation algorithms on scalable, hierarchically defined test casesFull-text access may be available. Sign in or learn about subscription options.pp. 698,699,700,701,702,703,704,705
by W.H. Nicholls, A.W. Nordsieck, M. Soma
Parallel pattern fault simulation based on stem faults in combinational circuitsFull-text access may be available. Sign in or learn about subscription options.pp. 706,707,708,709,710,711
by O. Song, P.R. Menon
An experimental study on reject ratio prediction for VLSI circuits: Kokomo revisitedFull-text access may be available. Sign in or learn about subscription options.pp. 712,713,714,715,716,717,718,719,720
by D.V. Das, S.C. Seth, P.T. Wagner, J.C. Anderson, V.D. Agrawal
Extending binary searches to two and three dimensions (IC testing)Full-text access may be available. Sign in or learn about subscription options.pp. 721,722,723,724,725
by R.L. Hickling
AC product defect level and yield lossFull-text access may be available. Sign in or learn about subscription options.pp. 726,727,728,729,730,731,732,733,734,735,736,737,738
by J. Savir
Macro-testability and the VSPFull-text access may be available. Sign in or learn about subscription options.pp. 739,740,741,742,743,744,745,746,747,748
by R. Mehtani, K. Baker, C.M. Huizer, P.J. Hynes, J. van Beers
Testability features of the 68040Full-text access may be available. Sign in or learn about subscription options.pp. 749,750,751,752,753,754,755,756,757
by M.G. Gallup, W. Ledbetter, R. McGarity, S. McMahan, K.C. Scheuer, C.G. Shepard, L. Sood
Fault grading the Intel 80486Full-text access may be available. Sign in or learn about subscription options.pp. 758,759,760,761
by N. Gollakota, A. Zaidi
Analysis of cellular automata used as pseudorandom pattern generatorsFull-text access may be available. Sign in or learn about subscription options.pp. 762,763,764,765,766,767,768
by P.H. Bardell
Cellular automata based self-test for programmable data pathsFull-text access may be available. Sign in or learn about subscription options.pp. 769,770,771,772,773,774,775,776,777,778
by J. van Sas, F. Catthoor, H. De Man
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