Proceedings International Test Conference 1998 (IEEE Cat. No.98CH36270)
Oct. 18 1998 to Oct. 23 1998
Washington, D.C. USA
ISSN: 1089-3539
ISBN: 0-7803-5093-6
Table of Contents
SESSION 1: PLENARY
SESSION 2: ESCAPING THE HIGH COST OF TEST ESCAPES
SESSION 2: ESCAPING THE HIGH COST OF TEST ESCAPES
SESSION 2: ESCAPING THE HIGH COST OF TEST ESCAPES
SESSION 3: MEMORY TEST ALGORITHMS AND PATTERN GENERATION
SESSION 3: MEMORY TEST ALGORITHMS AND PATTERN GENERATION
SESSION 3: MEMORY TEST ALGORITHMS AND PATTERN GENERATION
SESSION 4: DFT IN PRACTICE
SESSION 5: THERMAL ISSUES IN MANUFACTURING TEST
SESSION 5: THERMAL ISSUES IN MANUFACTURING TEST
SESSION 5: THERMAL ISSUES IN MANUFACTURING TEST
SESSION 7: BIST SYNTHESIS
SESSION 8: EXPERIMENTAL RESULTS IN CURRENT TESTING
SESSION 8: EXPERIMENTAL RESULTS IN CURRENT TESTING
SESSION 8: EXPERIMENTAL RESULTS IN CURRENT TESTING
SESSION 9: MCM TESTmdash;THEORY AND APPLICATIONS
SESSION 9: MCM TESTmdash;THEORY AND APPLICATIONS
SESSION 9: MCM TESTmdash;THEORY AND APPLICATIONS
SESSION 9: MCM TESTmdash;THEORY AND APPLICATIONS
SESSION 10: MIXED-SIGNAL TEST TECHNIQUES
SESSION 10: MIXED-SIGNAL TEST TECHNIQUES
SESSION 10: MIXED-SIGNAL TEST TECHNIQUES
SESSION 11: INTEGRATED PROBE CARD/INTERFACE SOLUTIONS FOR SPECIFIC TEST APPLICATIONS
SESSION 11: INTEGRATED PROBE CARD/INTERFACE SOLUTIONS FOR SPECIFIC TEST APPLICATIONS
SESSION 11: INTEGRATED PROBE CARD/INTERFACE SOLUTIONS FOR SPECIFIC TEST APPLICATIONS
SESSION 11: INTEGRATED PROBE CARD/INTERFACE SOLUTIONS FOR SPECIFIC TEST APPLICATIONS
SESSION 12: ACCESS AND TEST APPROACHES FOR EMBEDDED CORES
SESSION 12: ACCESS AND TEST APPROACHES FOR EMBEDDED CORES
SESSION 12: ACCESS AND TEST APPROACHES FOR EMBEDDED CORES
SESSION 12: ACCESS AND TEST APPROACHES FOR EMBEDDED CORES
SESSION 13: TEST SYNTHESIS
SESSION 13: TEST SYNTHESIS
SESSION 13: TEST SYNTHESIS
SESSION 14: TRANSISTOR LEVEL TEST TECHNIQUES
SESSION 14: TRANSISTOR LEVEL TEST TECHNIQUES
SESSION 14: TRANSISTOR LEVEL TEST TECHNIQUES
SESSION 15: BOARD AND SYSTEM TEST
SESSION 17: INTRODUCTION TO MEMS
SESSION 18: ADVANCES IN EMBEDDED CORE TEST
SESSION 18: ADVANCES IN EMBEDDED CORE TEST
SESSION 18: ADVANCES IN EMBEDDED CORE TEST
SESSION 19: MICROPROCESSOR TESTING
SESSION 19: MICROPROCESSOR TESTING
SESSION 20: ATE ARCHITECTURES: COST, IDDQ AND MIXED-SIGNAL ISSUES
SESSION 20: ATE ARCHITECTURES: COST, IDDQ AND MIXED-SIGNAL ISSUES
SESSION 20: ATE ARCHITECTURES: COST, IDDQ AND MIXED-SIGNAL ISSUES
SESSION 21: CONCURRENT CHECKING
SESSION 21: CONCURRENT CHECKING
SESSION 22: MEMS FAULT MODELING AND DIAGNOSIS
SESSION 22: MEMS FAULT MODELING AND DIAGNOSIS
SESSION 23: TEST CREATION FOR IMPLICITLY BURNING CORES
SESSION 23: TEST CREATION FOR IMPLICITLY BURNING CORES
SESSION 23: TEST CREATION FOR IMPLICITLY BURNING CORES
SESSION 24: REVOLUTION AND EVOLUTION IN TESTER SOFTWARE
SESSION 24: REVOLUTION AND EVOLUTION IN TESTER SOFTWARE
SESSION 24: REVOLUTION AND EVOLUTION IN TESTER SOFTWARE
SESSION 26: DFT THEORY
SESSION 26: DFT THEORY
SESSION 27: MIXED-SIGNAL DFT
SESSION 27: MIXED-SIGNAL DFT
SESSION 27: MIXED-SIGNAL DFT
SESSION 29: MICROPROCESSOR TEST TOOLS
SESSION 29: MICROPROCESSOR TEST TOOLS
SESSION 29: MICROPROCESSOR TEST TOOLS
SESSION 30: PUTTING THE ?DEFECT? IN DEFECT DIAGNOSIS
SESSION 30: PUTTING THE ?DEFECT? IN DEFECT DIAGNOSIS
SESSION 30: PUTTING THE ?DEFECT? IN DEFECT DIAGNOSIS