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2004 International Conferce on Test

Oct. 26 2004 to Oct. 28 2004

Charlotte, NC, USA

ISSN: 1089-3539

ISBN: 0-7803-8581-0

Table of Contents

Proceedings International Test Conference 2004 - Title PageFreely available from IEEE.pp. i-i
International Test Conference 2004 - Steering Committee and SubcommitteesFreely available from IEEE.pp. 2-3
In Memoriam Nathaniel "Ned" KornfieldFreely available from IEEE.pp. 4-4
ITC 2003 Paper AwardsFreely available from IEEE.pp. 5-5
ITC 2004 - Technical Program CommitteeFreely available from IEEE.pp. 6-8
International Test Conference 2004 - Technical Program CommitteeFreely available from IEEE.pp. 9-9
ITC technical paper evaluation and selection processFull-text access may be available. Sign in or learn about subscription options.pp. 10-10
International Test Conference 2005 - Call for PapersFreely available from IEEE.pp. 11-11
Test in the era of "What you see is not what you get" - Keynote addressFull-text access may be available. Sign in or learn about subscription options.pp. 12-12
by B. Koenemann
New test paradigms for yield and manufacturability - Invited addressFull-text access may be available. Sign in or learn about subscription options.pp. 13-13
by Robert Madge
TTTC: Test Technology Technical CouncilFreely available from IEEE.pp. 14-16
International Test Conference - 2004 Technical Paper ReviewersFreely available from IEEE.pp. 17-22
AC IO loopback design for high speed /spl mu/processor IO testFull-text access may be available. Sign in or learn about subscription options.pp. 23-30
by B. Provost, T. Huang, C.H. Lim, K. Tian, M. Bashir, M. Atha, A. Muhtaroglu, C. Zhao, H. Muljono
Cover
International Test Conference - Title PageFreely available from IEEE.pp. i
On correlating structural tests with functional tests for speed binning of high performance designFull-text access may be available. Sign in or learn about subscription options.pp. 31-37
by J. Zeng, M. Abadir, G. Vandling, L. Wang, A. Kolhatkar, J. Abraham
Cover
International Test Conference - CopyrightFreely available from IEEE.pp. iv
An optimized DFT and test pattern generation strategy for an Intel high performance microprocessorFull-text access may be available. Sign in or learn about subscription options.pp. 38-47
by D.M. Wu, M. Lin, M. Reddy, T. Jaber, A. Sabbavarapu, L. Thatcher
Introduction
Welcoming MessageFreely available from IEEE.pp. 1
Efficient pattern mapping for deterministic logic BISTFull-text access may be available. Sign in or learn about subscription options.pp. 48-56
by V. Gherman, H.-J. Wunderlich, H. Vranken, F. Hapke, M. Wittke, M. Garbers
Introduction
Steering Committee and SubcommitteesFreely available from IEEE.pp. 2
Introduction
Ned Kornfield MemorialFreely available from IEEE.pp. 4
Logic BIST with scan chain segmentationFull-text access may be available. Sign in or learn about subscription options.pp. 57-66
by Liyang Lai, J.H. Patel, T. Rinderknecht, Wu-Tung Cheng
Introduction
2003 Paper AwardsFull-text access may be available. Sign in or learn about subscription options.pp. 5
Spectral analysis for statistical response compaction during built-in self-testingFull-text access may be available. Sign in or learn about subscription options.pp. 67-76
by Omar Khan, M.L. Bushnell
A real-time jitter measurement board for high-performance computer and communication systemsFull-text access may be available. Sign in or learn about subscription options.pp. 77-84
by T.J. Yamaguchi, M. Ishida, M. Soma, K. Ichiyama, K. Christian, K. Ohsawa, M. Sugai
Introduction
Technical Program CommitteeFreely available from IEEE.pp. 6
Experimental results for high-speed jitter measurement techniqueFull-text access may be available. Sign in or learn about subscription options.pp. 85-94
by K. Taylor, B. Nelson, A. Chong, H. Nguyen, H. Lin, M. Soma, H. Haggag, J. Huard, J. Braatz
Introduction
ITC Technical Paper Evaluation and Selection ProcessFreely available from IEEE.pp. 10
An automated, complete, structural test solution for SERDESFull-text access may be available. Sign in or learn about subscription options.pp. 95-104
by S. Sunter, A. Roy, J.-F. Cote
Introduction
2005 Call for PapersFreely available from IEEE.pp. 11
Introduction
TTTC: Test Technology Technical CouncilFreely available from IEEE.pp. 14
A design for test technique for parametric analysis of SRAM: on-die low yield analysisFull-text access may be available. Sign in or learn about subscription options.pp. 105-113
by B.M. Mauck, V. Ravichandran, U.A. Mughal
Detecting faults in the peripheral circuits and an evaluation of SRAM testsFull-text access may be available. Sign in or learn about subscription options.pp. 114-123
by Ad.J. van de Goor, S. Hamdioui, R. Wadsworth
Introduction
Technical Paper ReviewersFreely available from IEEE.pp. 17
SESSION 1: PLENARY
Test In the Era of "What You see Is NOT What You Get"Freely available from IEEE.pp. 12
by Bernd Koenemann
MRAM defect analysis and fault modelingFull-text access may be available. Sign in or learn about subscription options.pp. 124-133
by Chin-Lung Su, Rei-Fu Huang, Cheng-Wen Wu, Chien-Chung Hung, Ming-Jer Kao, Yeong-Jar Chang, Wen-Ching Wu
SESSION 1: PLENARY
New Test Paradigms for Yield and ManufacturabilityFull-text access may be available. Sign in or learn about subscription options.pp. 13
by Robert Madge
CMOS IC diagnostics using the luminescence of off-state leakage currentsFull-text access may be available. Sign in or learn about subscription options.pp. 134-139
by S. Polonsky, K.A. Jenkins, A. Weger, Shinho Cho
SESSION 2: MICROPROCESSOR TEST
AC IO Loopback Design for High Speed uProcessor IO TestFull-text access may be available. Sign in or learn about subscription options.pp. 23-30
by Benoit Provost, Chee How Lim, Mo Bashir, Ali Muhtaroglu, Tiffany Huang, Kathy Tian, Mubeen Atha, Cangsang Zhao, Harry Muljono
A novel scan chain diagnostics technique based on light emission from leakage currentFull-text access may be available. Sign in or learn about subscription options.pp. 140-147
by P. Song, F. Stellari, T. Xia, A.J. Weger
SESSION 2: MICROPROCESSOR TEST
On Correlating Structural Tests with Functional Tests for Speed Binning of High Performance DesignFull-text access may be available. Sign in or learn about subscription options.pp. 31-37
by J. Zeng, M. Abadir, A. Kolhatkar, G. Vandling, L. Wang, J. Abraham
Impact of negative bias temperature instability on product parametric driftFull-text access may be available. Sign in or learn about subscription options.pp. 148-155
by V. Reddy, J. Carulli, A. Krishnan, W. Bosch, B. Burgess
SESSION 2: MICROPROCESSOR TEST
An Optimized DFT and Test Pattern Generation Strategy for an Intel High Performance MicroprocessorFull-text access may be available. Sign in or learn about subscription options.pp. 38-47
by David M. Wu, Mike Lin, Madhukar Reddy, Talal Jaber, Anil Sabbavarapu, Larry Thatcher
At-speed interconnect test and diagnosis of external memories on a systemFull-text access may be available. Sign in or learn about subscription options.pp. 156-162
by H.C. Kim, H.-S. Jun, Xinli Gu, S.S. Chung
SESSION 3: LOGIC BIST
EFFICIENT PATTERN MAPPING FOR DETERMINISTIC LOGIC BISTFull-text access may be available. Sign in or learn about subscription options.pp. 48-56
by Valentin Gherman, Hans-Joachim Wunderlich, Harald Vranken, Friedrich Hapke, Michael Wittke, Michael Garbers
Interconnect test pattern generation algorithm for meeting device and global SSO limits with safe initial vectorsFull-text access may be available. Sign in or learn about subscription options.pp. 163-172
by K. Baker, M. Nourani
SESSION 3: LOGIC BIST
Logic BISTWith Scan Chain SegmentationFull-text access may be available. Sign in or learn about subscription options.pp. 57-66
by Liyang Lai, Janak H. Patel, Thomas Rinderknecht, Wu-Tung Cheng
Removing JTAG bottlenecks in system interconnect testFull-text access may be available. Sign in or learn about subscription options.pp. 173-180
by Hong-Shin Jun, S.S. Chung, S.H. Baeg
SESSION 3: LOGIC BIST
Spectral Analysis for Statistical Response Compaction During Built-In Self-TestingFull-text access may be available. Sign in or learn about subscription options.pp. 67-76
by Omar Khan, Michael L. Bushnell
ATE data collection - a comprehensive requirements proposal to maximize ROI of testFull-text access may be available. Sign in or learn about subscription options.pp. 181-189
by M. Rehani, D. Abercrombie, R. Madge, J. Teisher, J. Saw
Non-deterministic DUT behavior during functional testing of high speed serial busses: challenges and solutionsFull-text access may be available. Sign in or learn about subscription options.pp. 190-196
by J. Hops, B. Swing, B. Phelps, B. Sudweeks, J. Pane, J. Kinslow
SESSION 4: BIST FOR JITTER
A Real-Time Jitter Measurement Board for High-Performance Computer and Communication SystemsFull-text access may be available. Sign in or learn about subscription options.pp. 77-84
by Takahiro J. Yamaguchi, Masahiro Ishida, Kiyotaka Ichiyama, Mani Soma, Krawinkel Christian, Katsuaki Ohsawa, Masao Sugai
Divide and conquer based Fast Shmoo algorithmsFull-text access may be available. Sign in or learn about subscription options.pp. 197-202
by P. Patten
SESSION 4: BIST FOR JITTER
Experimental Results for High-Speed Jitter Measurement TechniqueFull-text access may be available. Sign in or learn about subscription options.pp. 85-94
by Karen Taylor, Bryan Nelson, Alan Chong, Hieu Nguyen, Henry Lin, Mani Soma, Hosam Haggag, Jeff Huard, Jim Braatz
In search of the optimum test set - adaptive test methods for maximum defect coverage and lowest test costFull-text access may be available. Sign in or learn about subscription options.pp. 203-212
by R. Madge, B. Benware, R. Turakhia, R. Daasch, C. Schuermyer, J. Ruffler
SESSION 4: BIST FOR JITTER
An Automated, Complete, Structural Test Solution for SERDESFull-text access may be available. Sign in or learn about subscription options.pp. 95-104
by Stephen Sunter, Aubin Roy, J-F Cote
On hazard-free patterns for fine-delay fault testingFull-text access may be available. Sign in or learn about subscription options.pp. 213-222
by B. Kruseman, A.K. Majhi, G. Gronthoud, S. Eichenberger
SESSION 5: MEMORY TESTING
A Design for Test Technique for Parametric Analysis of SRAM: On-Die Low Yield AnalysisFull-text access may be available. Sign in or learn about subscription options.pp. 105-113
by Benjamin M. Mauck, Vishnumohan Ravichandran, Usman Azeez Mughal
SESSION 5: MEMORY TESTING
DETECTING FAULTS IN THE PERIPHERAL CIRCUITS AND AN EVALUATION OF SRAM TESTSFull-text access may be available. Sign in or learn about subscription options.pp. 114-123
by Ad J. Van de Goor, Said Hamdioui, Rob Wadsworth
K longest paths per gate (KLPG) test generation for scan-based sequential circuitsFull-text access may be available. Sign in or learn about subscription options.pp. 223-231
by W. Qiu, Jing Wang, D.M.H. Walker, D. Reddy, Xiang Lu, Zhuo Li, Weiping Shi, H. Balachandran
SESSION 5: MEMORY TESTING
MRAM Defect Analysis and Fault ModeliFull-text access may be available. Sign in or learn about subscription options.pp. 124-133
by Chin-Lung Su, Rei-Fu Huang, Cheng-Wen Wu, Chien-Chung Hung, Ming-Jer Kao, Yeong-Jar Chang, Wen-Ching Wu
A critical path selection method for delay testingFull-text access may be available. Sign in or learn about subscription options.pp. 232-241
by S. Padmanaban, S. Tragoudas
SESSION 6: FAILURE CHARACTERIZATION METHODS FOR IC DIAGNOSIS
CMOS IC diagnostics using the luminescence of OFF-state leakage currentsFull-text access may be available. Sign in or learn about subscription options.pp. 134-139
by Stas Polonsky, Keith A. Jenkins, Alan Weger, Shinho Cho
Evaluating the effectiveness of detecting delay defects in the slack interval: a simulation studyFull-text access may be available. Sign in or learn about subscription options.pp. 242-251
by Haihua Yan, A.D. Singh
SESSION 6: FAILURE CHARACTERIZATION METHODS FOR IC DIAGNOSIS
A Novel Scan Chain Diagnostics Technique Based on Light Emission from Leakage CurrentFull-text access may be available. Sign in or learn about subscription options.pp. 140-147
by Peilin Song, Franco Stellari, Alan J. Weger, Tian Xia
Quasi-oscillation based test for improved prediction of analog performance parametersFull-text access may be available. Sign in or learn about subscription options.pp. 252-261
by A. Raghunathan, J.H. Chun, J.A. Abraham, A. Chatterjee
SESSION 6: FAILURE CHARACTERIZATION METHODS FOR IC DIAGNOSIS
IMPACT OF NEGATIVE BIAS TEMPERATURE INSTABILITY ON PRODUCT PARAMETRIC DRIFTFull-text access may be available. Sign in or learn about subscription options.pp. 148-155
by Vijay Reddy, John Carulli, Anand Krishnan, William Bosch, Brendan Burgess
On-chip impulse response generation for analog and mixed-signal testingFull-text access may be available. Sign in or learn about subscription options.pp. 262-270
by A. Singh, C. Patel, J. Plusquellic
SESSION 7: BOARD AND SYSTEM TEST: AT-SPEED AND BOUNCE-FREE
At-Speed Interconnect Test and Diagnosis of External Memories on a SystemFull-text access may be available. Sign in or learn about subscription options.pp. 156-162
by Heon C. Kim, Hong-Shin Jun, Xinli Gu, Sung S. Chung
Automatic linearity (IP3) test with built-in pattern generator and analyzerFull-text access may be available. Sign in or learn about subscription options.pp. 271-280
by F. Dai, C. Stroud, D. Yang, Shuying Qi
SESSION 7: BOARD AND SYSTEM TEST: AT-SPEED AND BOUNCE-FREE
Interconnect Test Pattern Generation Algorithm For Meeting Device and Global SSO Limits With Safe Initial VectorsFull-text access may be available. Sign in or learn about subscription options.pp. 163-172
by Kendrick Baker, Mehrdad Nourani
Extending the digital core-based test methodology to support mixed-signalFull-text access may be available. Sign in or learn about subscription options.pp. 281-289
by G. Seuren, T. Waayers
SESSION 7: BOARD AND SYSTEM TEST: AT-SPEED AND BOUNCE-FREE
Removing JTAG Bottlenecks in System Interconnect TestFull-text access may be available. Sign in or learn about subscription options.pp. 173-180
by Hong-Shin Jun, Sung S. Chung, Sang H. Baeg
Systematic defects in deep sub-micron technologiesFull-text access may be available. Sign in or learn about subscription options.pp. 290-299
by B. Kruseman, A. Majhi, C. Hora, S. Eichenberger, J. Meirlevede
SESSION 8: METHODS AND STRATEGIES FOR OPTIMAL TEST
ATE Data Collection - A comprehensive requirements proposal to maximize ROI of testFull-text access may be available. Sign in or learn about subscription options.pp. 181-189
by Manu Rehani, David Abercrombie, Robert Madge, Jim Teisher, Jason Saw
Minimum testing requirements to screen temperature dependent defectsFull-text access may be available. Sign in or learn about subscription options.pp. 300-308
by C. Schuermyer, J. Ruffler, R. Daasch, R. Madge
SESSION 8: METHODS AND STRATEGIES FOR OPTIMAL TEST
NON-DETERMINISTIC DUT BEHAVIOR DURING FUNCTIONAL TESTING OF HIGH SPEED SERIAL BUSSES: CHALLENGES AND SOLUTIONSFull-text access may be available. Sign in or learn about subscription options.pp. 190-196
by Jonathan Hops, Brian Swing, Brian Phelps, Bruce Sudweeks, John Pane, James Kinslow
Random and systematic defect analysis using IDDQ signature analysis for understanding fails and guiding test decisionsFull-text access may be available. Sign in or learn about subscription options.pp. 309-318
by P. Nigh, A. Gattiker
SESSION 8: METHODS AND STRATEGIES FOR OPTIMAL TEST
Divide and Conquer based Fast Shmoo algorithmsFull-text access may be available. Sign in or learn about subscription options.pp. 197-202
by Peter Patten
Defect detection under realistic leakage models using multiple I/sub DDQ/ measurementsFull-text access may be available. Sign in or learn about subscription options.pp. 319-328
by C. Patel, A. Singh, J. Plusquellic
SESSION 8: METHODS AND STRATEGIES FOR OPTIMAL TEST
IN SEARCH OF THE OPTIMUM TEST SET - ADAPTIVE TEST METHODS FOR MAXIMUM DEFECT COVERAGE AND LOWEST TEST COSTFull-text access may be available. Sign in or learn about subscription options.pp. 203-212
by Robert Madge, Brady Benware, Ritesh Turakhia, Robert Daasch, Chris Schuermyer, Jens Ruffler
Testing micropipelined asynchronous circuitsFull-text access may be available. Sign in or learn about subscription options.pp. 329-338
by M.L. King, K.K. Saluja
SESSION 9: IN SEARCH OF SMALL DELAY DEFECTS
On Hazard-free Patterns for Fine-delay Fault TestingFull-text access may be available. Sign in or learn about subscription options.pp. 213-222
by Bram Kruseman, Ananta K. Majhi, Guido Gronthoud, Stefan Eichenberger
Scan based side channel attack on dedicated hardware implementations of Data Encryption StandardFull-text access may be available. Sign in or learn about subscription options.pp. 339-344
by Bo Yang, Kaijie Wu, Ramesh Karri
A holistic parallel and hierarchical approach towards design-for-testFull-text access may be available. Sign in or learn about subscription options.pp. 345-354
by C.P. Ravikumar, G. Hetherington
SESSION 9: IN SEARCH OF SMALL DELAY DEFECTS
K Longest Paths Per Gate (KLPG) Test Generation for Scan-Based Sequential CircuitsFull-text access may be available. Sign in or learn about subscription options.pp. 223-231
by Wangqi Qiu, Jing Wang, D. M. H. Walker, Divya Reddy, Zhuo Li, Weiping Shi, Hari Balachandran
Minimizing power consumption in scan testing: pattern generation and DFT techniquesFull-text access may be available. Sign in or learn about subscription options.pp. 355-364
by K.M. Butler, J. Saxena, A. Jain, T. Fryars, J. Lewis, G. Hetherington
SESSION 9: IN SEARCH OF SMALL DELAY DEFECTS
A Critical Path Selection Method for Delay TestingFull-text access may be available. Sign in or learn about subscription options.pp. 232-241
by Saravanan Padmanaban, Spyros Tragoudas
A new probing technique for high-speed/high-density printed circuit boardsFull-text access may be available. Sign in or learn about subscription options.pp. 365-374
by K.P. Parker
SESSION 9: IN SEARCH OF SMALL DELAY DEFECTS
Evaluating the Effectiveness of Detecting Delay Defects in the Slack Interval: A Simulation StudyFull-text access may be available. Sign in or learn about subscription options.pp. 242-251
by Haihua Yan, Adit D. Singh
On-chip mixed-signal test structures re-used for board testFull-text access may be available. Sign in or learn about subscription options.pp. 375-383
by R. Schuttert, D.C.L. van Geest
SESSION 10: MIXED-SIGNAL BIST AND DFT
Quasi-Oscillation Based Test for Improved Prediction of Analog Performance ParametersFull-text access may be available. Sign in or learn about subscription options.pp. 252-261
by Ashwin Raghunathan, Ji Hwan Chun, Jacob A. Abraham, Abhijit Chatterjee
Test strategy cost model innovationsFull-text access may be available. Sign in or learn about subscription options.pp. 384-392
by C. Michel, R.D. Reinosa
SESSION 10: MIXED-SIGNAL BIST AND DFT
On-Chip Impulse Response Generation for Analog and Mixed-Signal TestingFull-text access may be available. Sign in or learn about subscription options.pp. 262-270
by Abhishek Singh, Chintan Patel, Jim Plusquellic
SESSION 10: MIXED-SIGNAL BIST AND DFT
AUTOMATIC LINEARITY (IP3) TEST WITH BUILT-IN PATTERN GENERATOR AND ANALYZERFull-text access may be available. Sign in or learn about subscription options.pp. 271-280
by Foster Dai, Charles Stroud, Dayu Yang, Shuying Qi
Production test effectiveness of combined automated inspection and ICT test strategiesFull-text access may be available. Sign in or learn about subscription options.pp. 393-402
by A. Verma, C. Robinson, S. Butkovich
SESSION 10: MIXED-SIGNAL BIST AND DFT
Extending the Digital Core-based Test Methodology to Support Mixed-SignalFull-text access may be available. Sign in or learn about subscription options.pp. 281-289
by Geert Seuren, Tom Waayers
Open architecture test system: system architecture and designFull-text access may be available. Sign in or learn about subscription options.pp. 403-412
by R. Rajsuman, M. Noriyuki
SESSION 11: ADVANCES IN TESTING FOR DEFECTS
Systematic Defects in Deep Sub-Micron TechnologiesFull-text access may be available. Sign in or learn about subscription options.pp. 290-299
by Bram Kruseman, Ananta Majhi, Camelia Hora, Stefan Eichenberger, Johan Meirlevede
Test programming environment in a modular, open architecture test systemFull-text access may be available. Sign in or learn about subscription options.pp. 413-422
by A. Pramanick, R. Krishnaswamy, M. Elston, T. Adachi, Harsanjeet Singh, B. Parnas, L. Chen
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