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Proceedings. Fifth International Workshop on System-on-Chip for Real-Time Applications

July 20 2005 to July 24 2005

Banff, Alberta, Canada

Table of Contents

IntroductionFreely available from IEEE.pp. xii,xiii,xiv,xv,xvi
Plenary
Open HW, Open Design SW, and the VC Ecosystem DilemmaFull-text access may be available. Sign in or learn about subscription options.pp. 3-6
Software/Hardware System Co-design
A Methodology for Hw/Sw Specification and Simulation at Multiple Levels of AbstractionFull-text access may be available. Sign in or learn about subscription options.pp. 24-29
Software/Hardware System Co-design
A Software/Hardware Platform for Rapid Prototyping of Video and Multimedia DesignsFull-text access may be available. Sign in or learn about subscription options.pp. 30-33
Software/Hardware System Co-design
The Software/Hardware Co-Debug Environment with EmulatorFull-text access may be available. Sign in or learn about subscription options.pp. 34-38
Manufacturing & Reliability
Generic Modeling of Non-planar Dielectrics for 2 1/2D Parasitic ExtractionFull-text access may be available. Sign in or learn about subscription options.pp. 64-69
Analog and Mixed-Signal IC Design
PLL-Based Fractional-N Frequency SynthesizersFull-text access may be available. Sign in or learn about subscription options.pp. 85-91
Analog and Mixed-Signal IC Design
A New Topology for Power Control of High Efficiency Class-E Switched Mode Power AmplifierFull-text access may be available. Sign in or learn about subscription options.pp. 92-95
Analog and Mixed-Signal IC Design
A CMOS Quality Factor Enhanced Parallel Resonant LC-Tank with Independent Q and Frequency Tuning for RF Integrated FiltersFull-text access may be available. Sign in or learn about subscription options.pp. 96-100
Analog and Mixed-Signal IC Design
A Novel Clock Recovery Scheme with Improved Jitter Tolerance for PAM4 SignalingFull-text access may be available. Sign in or learn about subscription options.pp. 101-106
Analog and Mixed-Signal IC Design
A Very Low-Power Flash A/D Converter Based on Cmos Inverter CircuitFull-text access may be available. Sign in or learn about subscription options.pp. 107-110
Analog and Mixed-Signal IC Design
Bidirectional Current-Mode Capacitor Multiplier in DC-DC Converter CompensationFull-text access may be available. Sign in or learn about subscription options.pp. 111-116
Analog and Mixed-Signal IC Design
Design of 12-bit 100-MHz Current-Steering DAC for SoC ApplicationsFull-text access may be available. Sign in or learn about subscription options.pp. 117-122
Analog and Mixed-Signal IC Design
A Power Efficient Decoder for 2GHz, 6-bit CMOS Flash-ADC ArchitectureFull-text access may be available. Sign in or learn about subscription options.pp. 123-126
Analog and Mixed-Signal IC Design
A Comprehensive Model for On-Chip Spiral InductorsFull-text access may be available. Sign in or learn about subscription options.pp. 127-131
Analog and Mixed-Signal IC Design
Design and Optimization of Low-Voltage Low-Power Quasi-Floating Gate Digital CircuitsFull-text access may be available. Sign in or learn about subscription options.pp. 132-136
Digital System Design for SoC
A Review of Common Receive-End Adaptive Equalization Schemes and Algorithms for a High-Speed Serial BackplaneFull-text access may be available. Sign in or learn about subscription options.pp. 149-153
Digital System Design for SoC
Sigma-Delta Noise Shaping for Digital-to-Frequency and Digital-to-RF-Amplitude ConversionFull-text access may be available. Sign in or learn about subscription options.pp. 154-159
Digital System Design for SoC
Improved Wideband Low Distortion Cascaded Delta-Sigma ModulatorFull-text access may be available. Sign in or learn about subscription options.pp. 160-164
Sensors
Noise Analysis of a CMOS Active Pixel Sensor for Tomographic MammographyFull-text access may be available. Sign in or learn about subscription options.pp. 167-171
Sensors
A Temperature, Supply Voltage Compensated Floating-Gate MOS Dosimeter Using V_TH ExtractorFull-text access may be available. Sign in or learn about subscription options.pp. 176-179
Sensors
A pH-ISFET Based Micro Sensor System on Chip Using Standard CMOS TechnologyFull-text access may be available. Sign in or learn about subscription options.pp. 180-183
Sensors
A Very Low Power CMOS Potentiostat for Bioimplantable ApplicationsFull-text access may be available. Sign in or learn about subscription options.pp. 184-189
Multimedia IP Cores
An Acoustic Echo Canceller ChipFull-text access may be available. Sign in or learn about subscription options.pp. 193-198
Multimedia IP Cores
A High-Performance Error Concealment Processor for Video DecoderFull-text access may be available. Sign in or learn about subscription options.pp. 199-202
Multimedia IP Cores
A Scalable Low Power Imager Architecture for Compound-Eye Vision SensorsFull-text access may be available. Sign in or learn about subscription options.pp. 203-206
Multimedia IP Cores
UMHexagonS Algorithm Based Motion Estimation Architecture for H.264/AVCFull-text access may be available. Sign in or learn about subscription options.pp. 207-210
Multimedia IP Cores
A Hardware-Accelerated Framework with IP-Blocks for Application in MPEG-4Full-text access may be available. Sign in or learn about subscription options.pp. 211-214
Wireless Systems
VHDL Simulation and Modeling of an All-Digital RF TransmitterFull-text access may be available. Sign in or learn about subscription options.pp. 233-238
Wireless Systems
Efficient Pattern-Based Emulation for IEEE 802.11a BasebandFull-text access may be available. Sign in or learn about subscription options.pp. 239-242
Wireless Systems
A 2.3GHz CMOS Transimpedance Preamplifier for Optical CommunicationFull-text access may be available. Sign in or learn about subscription options.pp. 243-246
Wireless Systems
A 0.65V, 1.9mW CMOS Low-Noise Amplifier at 5GHzFull-text access may be available. Sign in or learn about subscription options.pp. 247-251
Wireless Systems
Design Mapping, and Simulations of a 3G WCDMA/FDD Basestation Using Network on ChipFull-text access may be available. Sign in or learn about subscription options.pp. 252-256
Wireless Systems
A Tier 3 Software Defined AM RadioFull-text access may be available. Sign in or learn about subscription options.pp. 257-261
VLSI Physical Design
A Stochastic Power-Supply Noise Reduction Technique Using Max-Flow Algorithm and Decoupling CapacitanceFull-text access may be available. Sign in or learn about subscription options.pp. 265-269
VLSI Physical Design
A Structure Based Clustering Algorithm with Applications to VLSI Physical DesignFull-text access may be available. Sign in or learn about subscription options.pp. 270-274
VLSI Physical Design
Global Lower Bounds for the VLSI Macrocell Floorplanning Problem Using Semidefinite OptimizationFull-text access may be available. Sign in or learn about subscription options.pp. 275-280
Towards SoC Design Automation Tools for SoC
Enhancing Performance and Saving Energy in CMOS DCVSL Gates by Using a New Transistor Sizing AlgorithmFull-text access may be available. Sign in or learn about subscription options.pp. 283-288
Towards SoC Design Automation Tools for SoC
Component-Based Methodology for Hardware Design of a Dataflow Processing NetworkFull-text access may be available. Sign in or learn about subscription options.pp. 289-294
Towards SoC Design Automation Tools for SoC
An automatic layout generator for I/O cellsFull-text access may be available. Sign in or learn about subscription options.pp. 295-300
Towards SoC Design Automation Tools for SoC
Additional Knowledge of Bus Invert Coding SchemesFull-text access may be available. Sign in or learn about subscription options.pp. 301-303
Towards SoC Design Automation Tools for SoC
High Level Extraction of SoC Architectural Information from Generic C Algorithmic DescriptionsFull-text access may be available. Sign in or learn about subscription options.pp. 304-307
Towards SoC Design Automation Tools for SoC
Practical Techniques for Performance Estimation of ProcessorsFull-text access may be available. Sign in or learn about subscription options.pp. 308-311
Towards SoC Design Automation Tools for SoC
A Multivalue Eigenvalue Based Circuit Partitioning TechniqueFull-text access may be available. Sign in or learn about subscription options.pp. 312-316
Towards SoC Design Automation Tools for SoC
A Hybrid Distributed Test Generation Method Using Deterministic and Genetic AlgorithmsFull-text access may be available. Sign in or learn about subscription options.pp. 317-322
Low-Power SoC
A Precise Model for Leakage Power Estimation in VLSI CircuitsFull-text access may be available. Sign in or learn about subscription options.pp. 337-340
Low-Power SoC
Turbo Codes — Digital IC DesignFull-text access may be available. Sign in or learn about subscription options.pp. 341-346
Low-Power SoC
A Low Area and Low Power Programmable Baseband Processor ArchitectureFull-text access may be available. Sign in or learn about subscription options.pp. 347-351
Low-Power SoC
Power Saving of a Dynamic Width Controller for a Monolithic Current-Mode CMOS DC-DC ConverterFull-text access may be available. Sign in or learn about subscription options.pp. 352-357
Low-Power SoC
An Optimal ILP Model for Delay Time to Minimize Peak Power and AreaFull-text access may be available. Sign in or learn about subscription options.pp. 358-362
Low-Power SoC
Power Reduction Technique Using Multi-vt LibrariesFull-text access may be available. Sign in or learn about subscription options.pp. 363-367
Low-Power SoC
A Low-Power Partitioning Methodology by Maximizing Sleep Time and Minimizing Cut NetsFull-text access may be available. Sign in or learn about subscription options.pp. 368-371
Low-Power SoC
An Area-Efficient High-Speed AES S-Box MethodFull-text access may be available. Sign in or learn about subscription options.pp. 376-379
Low-Power SoC
Low Latency and Power Efficient VD Using Register Exchanged State-Mapping AlgorithmFull-text access may be available. Sign in or learn about subscription options.pp. 380-384
Digital IP Cores
A Novel Design of a 6-GHz 8 X 8-b Pipelined MultiplierFull-text access may be available. Sign in or learn about subscription options.pp. 387-391
Digital IP Cores
An Area-Reduced Scheme for Modulo 2ⁿ-1 Addition/SubtractionFull-text access may be available. Sign in or learn about subscription options.pp. 396-399
Digital IP Cores
Very High Radix Scalable Montgomery MultipliersFull-text access may be available. Sign in or learn about subscription options.pp. 400-404
Digital IP Cores
A Fast Full Search Equivalent Encoding Algorithm for Image Vector Quantization Based on the WHT and a LUTFull-text access may be available. Sign in or learn about subscription options.pp. 405-409
Programmable and Reconfigurable Cores
An FPGA Based Accelerator for SAT Based Combinational Equivalence CheckingFull-text access may be available. Sign in or learn about subscription options.pp. 419-424
Programmable and Reconfigurable Cores
A Field-Programmable Analog Array Using Translinear ElementsFull-text access may be available. Sign in or learn about subscription options.pp. 425-428
Programmable and Reconfigurable Cores
Hardware Acceleration of Deadlock Avoidance and Detection in Real-Time Operating SystemsFull-text access may be available. Sign in or learn about subscription options.pp. 429-433
Programmable and Reconfigurable Cores
System-Level Analog Simulation of a Mixed-Signal Continuous-Time Field Programmable Analog ArrayFull-text access may be available. Sign in or learn about subscription options.pp. 434-438
Programmable and Reconfigurable Cores
FPGA Implementation of Digital Controller for DC-DC Buck ConverterFull-text access may be available. Sign in or learn about subscription options.pp. 439-443
Programmable and Reconfigurable Cores
Systolic Array-Based String Matching Unit for Spam BlockingFull-text access may be available. Sign in or learn about subscription options.pp. 444-449
Programmable and Reconfigurable Cores
An FPGA Design of a Unified Hash Engine for IPSec AuthenticationFull-text access may be available. Sign in or learn about subscription options.pp. 450-453
Programmable and Reconfigurable Cores
Performance Improvement of Configurable Processor Architectures Using a Variable Clock PeriodFull-text access may be available. Sign in or learn about subscription options.pp. 454-458
Programmable and Reconfigurable Cores
Programmable Low Dropout Voltage RegulatorFull-text access may be available. Sign in or learn about subscription options.pp. 459-462
Emerging Issue
Simulation and Analysis of Network on Chip Architecture for Wireless Communication SystemFull-text access may be available. Sign in or learn about subscription options.pp. 471-475
IP-Blocks for Broadband Networking
Decision Feedback Equalization with Quarter-Rate Clock Timing for High-Speed Backplane Data CommunicationsFull-text access may be available. Sign in or learn about subscription options.pp. 500-502
IP-Blocks for Broadband Networking
A High Efficiency 3GHz 24-dBm CMOS Linear Power Amplifier for RF ApplicationFull-text access may be available. Sign in or learn about subscription options.pp. 503-507
IP-Blocks for Broadband Networking
A 20 Gbps Scalable Load-Balanced TDM Switch with CODEC for High Speed Networking ApplicationsFull-text access may be available. Sign in or learn about subscription options.pp. 508-513
MPSOC
Synchronous Pipelined Relay Stations with Back-Pressure ToleranceFull-text access may be available. Sign in or learn about subscription options.pp. 517-520
MPSOC
Modular Architecture for System-on-Chip Design of Scalable MEMS Optical Switch Actuator ControllerFull-text access may be available. Sign in or learn about subscription options.pp. 521-524
MPSOC
Architecture for Multi-processor SoC Platform Using Dedicated ChannelsFull-text access may be available. Sign in or learn about subscription options.pp. 525-529
MPSOC
Implementation of an On-Chip Bus Bridge between Heterogeneous Buses with Different Clock FrequenciesFull-text access may be available. Sign in or learn about subscription options.pp. 530-534
MPSOC
Traffic Configuration for Evaluating Networks on ChipsFull-text access may be available. Sign in or learn about subscription options.pp. 535-540
MPSOC
Orthogonalized Communication Architecture for MP-SoC with Global BusFull-text access may be available. Sign in or learn about subscription options.pp. 541-545
MPSOC
MP SoCs Including Optical Interconnect. Technological Progresses and Challenges for CAD Tools DesignFull-text access may be available. Sign in or learn about subscription options.pp. 546-551
MPSOC
Transaction Analysis of Multiprocessor Based Platform with Bus MatrixFull-text access may be available. Sign in or learn about subscription options.pp. 552-556
MPSOC
A Generic Method for Embedded Measurement and Compensation of Process and Temperature Variations in SoCsFull-text access may be available. Sign in or learn about subscription options.pp. 557-562
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