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Sixth ACM and IEEE International Conference on Formal Methods and Models for Co-design, MEMOCODE '08

June 5 2008 to June 7 2008

Anaheim, CA

Table of Contents

[Title page - 2008 6th ACM/IEEE International Conference on Formal Methods and Models for Co-Design]Freely available from IEEE.
Copyright statement [2008 6th ACM/IEEE International Conference on Formal Methods and Models for Co-Design]Freely available from IEEE.
[Commentary]Freely available from IEEE.
Contributor listingsFreely available from IEEE.
Table of contentsFreely available from IEEE.
Breaker Pages: Keynote Talk IFreely available from IEEE.
Programming Multicores with Kahn Process Networks; a Smart Choice?Full-text access may be available. Sign in or learn about subscription options.
by Bart Kienhuis
Breaker Pages - Session I: Formal VerificationFreely available from IEEE.
Arithmetic Circuits Verification without Looking for Internal EquivalencesFull-text access may be available. Sign in or learn about subscription options.
by O. Sarbishei, B. Alizadeh, Masahiro Fujita
From Data to Events: Checking Properties on the Control of a SystemFull-text access may be available. Sign in or learn about subscription options.
by Christophe Jacquet, Frederic Boulanger, Dominique Marcadet
Vacuity Analysis by Fault SimulationFull-text access may be available. Sign in or learn about subscription options.
by Luigi di Guglielmo, Franco Fummi, Graziano Pravadelli
Breaker Pages - Session II: Semantics of System Description LanguagesFreely available from IEEE.
Rule-Based Approaches for Equivalence Checking of SpecC ProgramsFull-text access may be available. Sign in or learn about subscription options.
by Subash Shankar, Masahiro Fujita
Static Deadlock Detection for the SHIM Concurrent LanguageFull-text access may be available. Sign in or learn about subscription options.
by Nalini Vasudevan, Stephen A. Edwards
A Comparison of Two SystemC/TLM Semantics for Formal VerificationFull-text access may be available. Sign in or learn about subscription options.
by Claude Helmstetter, Olivier Ponsini
Poster session [breaker pages]Freely available from IEEE.
Latency-Insensitive Hardware/Software InterfacesFull-text access may be available. Sign in or learn about subscription options.
by Greg Hoover, Forrest Brewer, Chris Gill
Bisimulator 2.0: An On-the-Fly Equivalence Checker based on Boolean Equation SystemsFull-text access may be available. Sign in or learn about subscription options.
by Radu Mateescu, Emilie Oudot
Assertion-Based Design with HorusFull-text access may be available. Sign in or learn about subscription options.
by Yann Oddos, Katell Morin-Allory, Dominique Borrione
Breaker Pages - Session IV: Tools and Techniques for Processor DesignFreely available from IEEE.
A System Verilog Rewriting System for RTL Abstraction with Pentium Case StudyFull-text access may be available. Sign in or learn about subscription options.
by Steve Haynal, Timothy Kam, Michael Kishinevsky, Emily Shriver, Xinning Wang
Directed-Logical Testing for Functional Verification of MicroprocessorsFull-text access may be available. Sign in or learn about subscription options.
by Michael Katelman, Jose Meseguer, Santiago Escobar
Estimating the Performance of Cache Replacement PoliciesFull-text access may be available. Sign in or learn about subscription options.
by Daniel Grund, Jan Reineke
Breaker Pages: Keynote Talk IIFreely available from IEEE.
Infinite State Model Checking with Arithmetic ConstraintsFull-text access may be available. Sign in or learn about subscription options.
by Tevfik Bultan
Session V: Models of ComputationFreely available from IEEE.
Classification of General Data Flow Actors into Known Models of ComputationFull-text access may be available. Sign in or learn about subscription options.
by Christian Zebelein, Joachim Falk, Christian Haubelt, Jurgen Teich
On the Deterministic Multi-threaded Software Synthesis from Polychronous SpecificationsFull-text access may be available. Sign in or learn about subscription options.
by Bijoy A. Jose, Sandeep K. Shukla, Hiren D. Patel, Jean-Pierre Talpin
Virtual prototyping AADL architectures in a polychronous model of computationFull-text access may be available. Sign in or learn about subscription options.
by Yue Ma, Jean-Pierre Talpin, Thierry Gautier
Breaker Pages - Session VI: Co-Design ContestFreely available from IEEE.
MEMOCODE 2008 Co-Design ContestFull-text access may be available. Sign in or learn about subscription options.
by Patrick Schaumont, Krste Asanovic, James C. Hoe
High-throughput Pipelined MergesortFull-text access may be available. Sign in or learn about subscription options.
by Kermin Fleming, Myron King, Man Cheuk Ng, Asif Khan, Muralidaran Vijayaraghavan
Hardware Accelerated Crypto Merge Sort: MEMOCODE 2008 Design ContestFull-text access may be available. Sign in or learn about subscription options.
by VJ Sananda
Breaker Pages - Session VII: Design Case StudiesFreely available from IEEE.
H.264 Decoder: A Case Study in Multiple Design PointsFull-text access may be available. Sign in or learn about subscription options.
by Kermin Fleming, Chun-Chieh Lin, Nirav Dave, Arvind, Gopal Raghavan, Jamey Hicks
Correctness of a Fault-Tolerant Real-Time Scheduler and its Hardware ImplementationFull-text access may be available. Sign in or learn about subscription options.
by Eyad Alkassar, Peter Bohm, Steffen Knapp
Specification and Verification of LambdaRAM- A Wide-area Distributed Cache for High Performance ComputingFull-text access may be available. Sign in or learn about subscription options.
by Venkatram Vishwanath, Lenore D. Zuck, Jason Leigh
Breaker Pages - Panel IFreely available from IEEE.
Breaker Pages - Panel: Methodologies for On-Chip Communication Design: Trends and ChallengesFreely available from IEEE.
Breaker Pages - Tutorial IFreely available from IEEE.
Hands-on Introduction to Bluespec System Verilog (BSV)Full-text access may be available. Sign in or learn about subscription options.
by Arvind, Rishiyur Nikhil
Author indexFreely available from IEEE.
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