1. Home
  2. Proceedings
  3. MICRO
  4. MICRO 1993
Default Cover Image

Proceedings of 26th Annual International Symposium on Microarchitecture (Cat. No.93TH0602-3)

Dec. 1 1993 to Dec. 3 1993

Austin, TX, USA

Table of Contents

Efficient scheduling of fine grain parallelism in loopsFull-text access may be available. Sign in or learn about subscription options.pp. 2-11
by M. Rajagopalan, V. H. Allan
Employing finite automata for resource schedulingFull-text access may be available. Sign in or learn about subscription options.pp. 12-20
by Thomas Müller
GPMB—software pipelining branch-intensive loopsFull-text access may be available. Sign in or learn about subscription options.pp. 21-30
by Zhihong Tang, Gang Chen, Chihong Zhang, Yingwei Zhang, Bogong Su, Stanley Habib
A microarchitectural performance evaluation of a 3.2 Gbyte/s microprocessor busFull-text access may be available. Sign in or learn about subscription options.pp. 31-40
by Tim Stanley, Michael Upton, Patrick Sherhart, Trevor Mudge, Richard Brown
Two-ported cache alternatives for superscalar processorsFull-text access may be available. Sign in or learn about subscription options.pp. 41-48
by Andrew Wolfe, Rodney Boleyn
A study on the number of memory ports in multiple instruction issue machinesFull-text access may be available. Sign in or learn about subscription options.pp. 49-59
by Soo-Mook Moon, Kemal Ebcioğlu
The 16-fold way: a microparallel taxonomyFull-text access may be available. Sign in or learn about subscription options.pp. 60-69
by Barton J. Sano, Alvin M. Despain
A comparative performance evaluation of various state maintenance mechanismsFull-text access may be available. Sign in or learn about subscription options.pp. 70-79
by Michael Butler, Yale Patt
Dynamically scheduled VLIW processorsFull-text access may be available. Sign in or learn about subscription options.pp. 80-92
by B. Ramakrishna Rau
Prophetic branches: a branch architecture for code compaction and efficient executionFull-text access may be available. Sign in or learn about subscription options.pp. 94-99
by Apoorv Srivastava, Alvin M. Despain
A comparision of superscalar and decoupled access/execute architecturesFull-text access may be available. Sign in or learn about subscription options.pp. 100-103
by Matthew K. Farrens, Pius Ng, Phil Nico
Measuring limits of parallelism and characterizing its vulnerability to resource constraintsFull-text access may be available. Sign in or learn about subscription options.pp. 105-117
by Lawrence Rauchwerger, Pradeep K. Dubey, Ravi Nair
An evaluation of bottom-up and top-down thread generation techniquesFull-text access may be available. Sign in or learn about subscription options.pp. 118-127
by A. P. W. Böhm, W. A. Najjar, B. Shankar, L. Roh
Techniques for extracting instruction level parallelism on MIMD architecturesFull-text access may be available. Sign in or learn about subscription options.pp. 128-137
by Gary Tyson, Matthew Farrens
Predictability of load/store instruction latenciesFull-text access may be available. Sign in or learn about subscription options.pp. 139-152
by Santosh G. Abraham, Rabin A. Sugumar, Daniel Windheiser, B. R. Rau, Rajiv Gupta
Control flow prediction for dynamic ILP processorsFull-text access may be available. Sign in or learn about subscription options.pp. 1-11
by Dionisios N. Pnevmatikatos, Manoj Franklin, Gurindar S. Sohi
Branch history table indexing to prevent pipeline bubbles in wide-issue superscalar processorsFull-text access may be available. Sign in or learn about subscription options.pp. 164-175
by Tse-Yu Yeh, Yale N. Patt
Clocked and asynchronous instruction pipelinesFull-text access may be available. Sign in or learn about subscription options.pp. 177-184
by Mark A. Franklin, Tienyo Pan
An analysis of dynamic scheduling techniques for symbolic applicationsFull-text access may be available. Sign in or learn about subscription options.pp. 185-191
by Alessandra Costa, Alessandro De Gloria, Paolo Faraboschi, Mauro Olivieri
MIDEE: smoothing branch and instruction cache miss penalties on deep pipelinesFull-text access may be available. Sign in or learn about subscription options.pp. 193-201
by Nathalie Drach, André Seznec
Register renaming and dynamic speculation: an alternative approachFull-text access may be available. Sign in or learn about subscription options.pp. 202-213
by Mayan Moudgill, Keshav Pingali, Stamatis Vassiliadis
Speculative execution exception recovery using write-back suppressionFull-text access may be available. Sign in or learn about subscription options.pp. 214-223
by Roger A. Bringmann, Scott A. Mahlke, Richard E. Hank, John C. Gyllenhaal, Wen-mei W. Hwu
EXPLORER: a retargetable and visualization-based trace-driven simulator for superscalar processorsFull-text access may be available. Sign in or learn about subscription options.pp. 225-235
by Trung A. Diep, John P. Shen, Mike Phillip
An extended classification of inter-instruction dependency and its application in automatic synthesis of pipelined processorsFull-text access may be available. Sign in or learn about subscription options.pp. 236-246
by Ing-Jer Huang, Alvin M. Despain
Superblock formation using static program analysisFull-text access may be available. Sign in or learn about subscription options.pp. 247-255
by Richard E. Hank, Scott A. Mahlke, Roger A. Bringmann, John C. Gyllenhaal, Wen-mei W. Hwu
Instruction scheduling for the Motorola 88110Full-text access may be available. Sign in or learn about subscription options.pp. 257-262
by Mark Smotherman, Shuchi Chawla, Stan Cox, Brian Malloy
A VLIW architecture based on shifting register filesFull-text access may be available. Sign in or learn about subscription options.pp. 263-268
by H. Fatih Uğurdağ, Christos A. Papachristou
Proceedings of 26th Annual International Symposium on Microarchitecture (Cat. No.93TH0602-3)Freely available from IEEE.pp. 0_1
Showing 28 out of 28