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Proceedings of MICRO'95: 28th Annual IEEE/ACM International Symposium on Microarchitecture

Nov. 29 1995 to Dec. 1 1995

Ann Arbor, MI, USA

Table of Contents

[Front matter]Freely available from IEEE.pp. 3-14
Keynote addressFreely available from IEEE.pp. 1-2
by R.I. Baum
Performance issues in correlated branch prediction schemesFull-text access may be available. Sign in or learn about subscription options.pp. 3-14
by N. Gloy, M.D. Smith, C. Young
Dynamic path-based branch correlationFull-text access may be available. Sign in or learn about subscription options.pp. 15-23
by R. Nair
The predictability of branches in librariesFull-text access may be available. Sign in or learn about subscription options.pp. 24-34
by B. Calder, D. Grunwald, A. Srivastava
The performance impact of incomplete bypassing in processor pipelinesFull-text access may be available. Sign in or learn about subscription options.pp. 36-45
by P.S. Ahuja, D.W. Clark, A. Rogers
Efficient instruction scheduling using finite state automataFull-text access may be available. Sign in or learn about subscription options.pp. 46-56
by V. Bala, N. Rubin
Critical path reduction for scalar programsFull-text access may be available. Sign in or learn about subscription options.pp. 57-69
by M. Schlansker, V. Kathail
A limit study of local memory requirements using value reuse profilesFull-text access may be available. Sign in or learn about subscription options.pp. 71-81
by A.S. Huang, J.P. Shen
Zero-cycle loads: microarchitecture support for reducing load latencyFull-text access may be available. Sign in or learn about subscription options.pp. 82-92
by T.M. Austin, G.S. Sohi
A modified approach to data cache managementFull-text access may be available. Sign in or learn about subscription options.pp. 93-103
by G. Tyson, M. Farrens, J. Matthews, A.R. Pleszkun
Petri net versus module scheduling for software pipeliningFull-text access may be available. Sign in or learn about subscription options.pp. 105-110
by V.H. Allan, U.R. Shah, K.M. Reddy
Modulo scheduling with multiple initiation intervalsFull-text access may be available. Sign in or learn about subscription options.pp. 111-118
by N.J. Warter-Perez, N. Partamian
Spill-free parallel scheduling of basic blocksFull-text access may be available. Sign in or learn about subscription options.pp. 119-124
by B. Natarajan, M. Schlansker
Improving instruction-level parallelism by loop unrolling and dynamic memory disambiguationFull-text access may be available. Sign in or learn about subscription options.pp. 125-132
by J.W. Davidson, S. Jinturkar
Self-regulation of workload in the Manchester Data-Flow ComputerFull-text access may be available. Sign in or learn about subscription options.pp. 135-145
by J.R. Gurd, D.F. Snelling
The M-Machine multicomputerFull-text access may be available. Sign in or learn about subscription options.pp. 146-156
by M. Fillo, S.W. Keckler, W.J. Dally, N.P. Carter, A. Chang, Y. Gurevich, W.S. Lee
Region-based compilation: an introduction and motivationFull-text access may be available. Sign in or learn about subscription options.pp. 158-168
by R.E. Hank, W.W. Hwu, B.R. Rau
An experimental study of several cooperative register allocation and instruction scheduling strategiesFull-text access may be available. Sign in or learn about subscription options.pp. 169-179
by C. Norris, L.L. Pollock
Register allocation for predicated codeFull-text access may be available. Sign in or learn about subscription options.pp. 180-191
by A.E. Eichenberger, E.S. Davidson
Partial resolution in branch target buffersFull-text access may be available. Sign in or learn about subscription options.pp. 193-198
by B. Fagin, K. Russell
A system level perspective on branch architecture performanceFull-text access may be available. Sign in or learn about subscription options.pp. 199-206
by B. Calder, D. Grunwald, J. Emer
Dynamic rescheduling: a technique for object code compatibility in VLIW architecturesFull-text access may be available. Sign in or learn about subscription options.pp. 208-218
by T.M. Conte, S.W. Sathaye
Improving CISC instruction decoding performance using a fill unitFull-text access may be available. Sign in or learn about subscription options.pp. 219-229
by M. Smotherman, M. Franklin
SPAID: software prefetching in pointer- and call-intensive environmentsFull-text access may be available. Sign in or learn about subscription options.pp. 231-236
by M.H. Lipasti, W.J. Schmidt, S.R. Kunkel, R.R. Roediger
An effective programmable prefetch engine for on-chip cachesFull-text access may be available. Sign in or learn about subscription options.pp. 237-242
by Tien-Fu Chen
Cache miss heuristics and preloading techniques for general-purpose programsFull-text access may be available. Sign in or learn about subscription options.pp. 243-248
by T. Ozawa, Y. Kimura, S. Nishizaki
Alternative implementations of hybrid branch predictorsFull-text access may be available. Sign in or learn about subscription options.pp. 252-257
by Po-Yung Chang, E. Hao, Y.N. Patt
Control flow prediction with tree-like subgraphs for superscalar processorsFull-text access may be available. Sign in or learn about subscription options.pp. 258-263
by S. Dutta, M. Franklin
The role of adaptivity in two-level adaptive branch predictionFull-text access may be available. Sign in or learn about subscription options.pp. 264-269
by S. Sechrest, Chih-Chieh Lee, T. Mudge
Design of storage hierarchy in multithreaded architecturesFull-text access may be available. Sign in or learn about subscription options.pp. 271-278
by L. Roh, W.A. Najjar
An investigation of the performance of various instruction-issue buffer topologiesFull-text access may be available. Sign in or learn about subscription options.pp. 279-284
by S. Jourdan, P. Sainrat, D. Litaize
Decoupling integer execution in superscalar processorsFull-text access may be available. Sign in or learn about subscription options.pp. 285-290
by S. Palacharla, J.E. Smith
Exploiting short-lived variables in superscalar processorsFull-text access may be available. Sign in or learn about subscription options.pp. 292-302
by L.A. Lozano, G.R. Gao
Partitioned register file for TTAsFull-text access may be available. Sign in or learn about subscription options.pp. 303-312
by J. Janssen, H. Corporaal
Disjoint eager execution: an optimal form of speculative executionFull-text access may be available. Sign in or learn about subscription options.pp. 313-325
by A.K. Uht, V. Sindagi, K. Hall
Unrolling-based optimizations for modulo schedulingFull-text access may be available. Sign in or learn about subscription options.pp. 327-337
by D.M. Lavery, W.-W. Hwu
Stage scheduling: a technique to reduce the register requirements of a module scheduleFull-text access may be available. Sign in or learn about subscription options.pp. 338-349
by A.E. Eichenberger, E.S. Davidson
Hypernode reduction modulo schedulingFull-text access may be available. Sign in or learn about subscription options.pp. 350-360
by J. Llosa, M. Valero, E. Ayguade, A. Gonzalez
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