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Proceedings
MICRO
MICRO 1996
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Proceedings of the 29th Annual IEEE/ACM International Symposium on Microarchitecture. MICRO 29
Dec. 2 1996 to Dec. 4 1996
Paris, FRANCE
ISSN: 1072-4451
ISBN: 0-8186-7641-8
Table of Contents
IEEE/ACM International Symposium on Microarchitecture Micro-29
Freely available from IEEE.
pp. iii,iv,v,vi,vii
Preface
Freely available from IEEE.
pp. viii
Program and Steering Committee
Freely available from IEEE.
pp. ix
Referees
Freely available from IEEE.
pp. xi
Session 1
A persistent rescheduled-page cache for low overhead object code compatibility in VLIW architectures
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pp. 4
by
T.M. Conte
,
S.W. Sathaye
,
S. Banerjia
Session 1
Integrating a misprediction recovery cache (MRC) into a superscalar pipeline
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pp. 14
by
J.O. Bondi
,
A.K. Nanda
,
S. Dutta
Session 1
Trace Cache: a Low Latency Approach to High Bandwidth Instruction Fetching
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pp. 24
by
Eric Rotenberg
,
Jim Smith
,
Steve Bennett
Session 2
Accurate and Practical Profile-Driven Compilation Using the Profile Buffer
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pp. 36
by
Thomas M. Conte
,
Kishore N. Menezes
,
Mary Ann Hirsch
Session 2
Efficient Path Profiling
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pp. 46
by
Thomas Ball
,
James R. Larus
Session 2
Profile-driven instruction level parallel scheduling with application to super blocks
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pp. 58
by
C. Chekuri
,
R. Johnson
,
R. Motwani
,
B. Natarajan
,
B.R. Rau
,
M. Schlansker
Session 3
Speculative Hedge: Regulating Compile-Time Speculation Against Profile Variations
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pp. 70
by
Brian L. Deitrich
,
Wen-mei W. Hwu
Session 3
Hot Cold Optimization of Large Windows/NT Applications
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pp. 80
by
Robert Cohn
,
P. Geoffrey Lowney
Session 3
Java Bytecode to Native Code Translation: The Caffeine Prototype and Preliminary Results
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pp. 90
by
Cheng-Hsueh A. Hsieh
,
John C. Gyllenhaal
,
Wen-mei W. Hwu
Session 4
Analysis techniques for predicated code
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pp. 100
by
R. Johnson
,
M. Schlansker
Session 4
Global Predicate Analysis and its Application to Register Allocation
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pp. 114
by
David M. Gillies
,
Dz-ching Roy Ju
,
Richard Johnson
,
Michael Schlansker
Proceedings Third IEEE Workshop on Applications of Computer Vision. WACV'96
Freely available from IEEE.
pp. 349-349
Session 4
Modulo Scheduling of Loops in Control-Intensive Non-Numeric Programs
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pp. 126
by
Daniel M. Lavery
,
Wen-mei W. Hwu
Session 5
Assigning confidence to conditional branch predictions
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pp. 142
by
E. Jacobsen
,
E. Rotenberg
,
J.E. Smith
Session 5
Compiler Synthesized Dynamic Branch Prediction
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pp. 153
by
Scott Mahlke
,
Balas Natarajan
Session 5
Wrong-Path Instruction Prefetching
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pp. 165
by
Jim Pierce
,
Trevor Mudge
Session 6
Design decisions influencing the UltraSPARC's instruction fetch architecture
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pp. 178
by
R. Yung
Session 6
Increasing the Instruction Fetch Rate via Block-Structured Instruction Set Architectures
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pp. 191
by
Eric Hao
,
Po-Yung Chang
,
Marius Evers
,
Yale N. Patt
Session 6
Instruction fetch mechanisms for VLIW architectures with compressed encodings
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pp. 201
by
T.M. Conte
,
S. Banerjia
,
S.Y. Larin
,
K.N. Menezes
,
S.W. Sathaye
Session 7
Tango: a hardware-based data prefetching technique for superscalar processors
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pp. 214
by
S.S. Pinter
,
A. Yoaz
Session 7
Exceeding the Dataflow Limit via Value Prediction
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pp. 226
by
Mikko H. Lipasti
,
John Paul Shen
Session 7
The performance potential of data dependence speculation and collapsing
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pp. 238
by
Y. Sazeides
,
S. Vassiliadis
,
J.E. Smith
Session 8
Heuristics for Register-constrained Software Pipelining
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pp. 250
by
Josep Llosa
Session 8
Software Pipelining Loops with Conditional Branches
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pp. 262
by
Mark G. Stoodley
,
Corinna G. Lee
Session 8
Combining loop transformations considering caches and scheduling
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pp. 274
by
M.E. Wolf
,
D.E. Maydan
,
Ding-Kai Chen
Session 9
Instruction Scheduling and Executable Editing
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pp. 288
by
Eric Schnarr
,
James R. Larus
Session 9
Instruction scheduling for the HP PA-8000
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pp. 298
by
D.A. Dunn
,
Wei-Chung Hsu
Session 9
Meld Scheduling: Relaxing Scheduling Constraints across Region Boundaries
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pp. 308
by
Santosh G. Abraham
,
Vinod Kathail
,
Brian L. Deitrich
Session 10
Custom--Fit Processors: Letting Applications Define Architectures
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pp. 324
by
Joseph A. Fisher
,
Paolo Faraboschi
,
Giuseppe Desoli
Session 10
Optimization for a Superscalar Out-of-Order Machine
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pp. 336
by
Anne M. Holler
Session 10
Optimization of Machine Descriptions for Efficient Use
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pp. 349
by
J.C. Gyllenhaal
,
W.W. Hwu
,
B.R. Rau
Session 10
Author Index
Freely available from IEEE.
pp. 359
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