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Proceedings of the 29th Annual IEEE/ACM International Symposium on Microarchitecture. MICRO 29

Dec. 2 1996 to Dec. 4 1996

Paris, FRANCE

ISSN: 1072-4451

ISBN: 0-8186-7641-8

Table of Contents

IEEE/ACM International Symposium on Microarchitecture Micro-29Freely available from IEEE.pp. iii,iv,v,vi,vii
PrefaceFreely available from IEEE.pp. viii
Program and Steering CommitteeFreely available from IEEE.pp. ix
RefereesFreely available from IEEE.pp. xi
Session 1
A persistent rescheduled-page cache for low overhead object code compatibility in VLIW architecturesFull-text access may be available. Sign in or learn about subscription options.pp. 4
Session 1
Integrating a misprediction recovery cache (MRC) into a superscalar pipelineFull-text access may be available. Sign in or learn about subscription options.pp. 14
Session 1
Trace Cache: a Low Latency Approach to High Bandwidth Instruction FetchingFull-text access may be available. Sign in or learn about subscription options.pp. 24
Session 2
Accurate and Practical Profile-Driven Compilation Using the Profile BufferFull-text access may be available. Sign in or learn about subscription options.pp. 36
Session 2
Efficient Path ProfilingFull-text access may be available. Sign in or learn about subscription options.pp. 46
Session 2
Profile-driven instruction level parallel scheduling with application to super blocksFull-text access may be available. Sign in or learn about subscription options.pp. 58
Session 3
Speculative Hedge: Regulating Compile-Time Speculation Against Profile VariationsFull-text access may be available. Sign in or learn about subscription options.pp. 70
Session 3
Hot Cold Optimization of Large Windows/NT ApplicationsFull-text access may be available. Sign in or learn about subscription options.pp. 80
Session 3
Java Bytecode to Native Code Translation: The Caffeine Prototype and Preliminary ResultsFull-text access may be available. Sign in or learn about subscription options.pp. 90
Session 4
Analysis techniques for predicated codeFull-text access may be available. Sign in or learn about subscription options.pp. 100
Session 4
Global Predicate Analysis and its Application to Register AllocationFull-text access may be available. Sign in or learn about subscription options.pp. 114
Session 4
Modulo Scheduling of Loops in Control-Intensive Non-Numeric ProgramsFull-text access may be available. Sign in or learn about subscription options.pp. 126
Session 5
Assigning confidence to conditional branch predictionsFull-text access may be available. Sign in or learn about subscription options.pp. 142
Session 5
Compiler Synthesized Dynamic Branch PredictionFull-text access may be available. Sign in or learn about subscription options.pp. 153
Session 5
Wrong-Path Instruction PrefetchingFull-text access may be available. Sign in or learn about subscription options.pp. 165
Session 6
Design decisions influencing the UltraSPARC's instruction fetch architectureFull-text access may be available. Sign in or learn about subscription options.pp. 178
Session 6
Increasing the Instruction Fetch Rate via Block-Structured Instruction Set ArchitecturesFull-text access may be available. Sign in or learn about subscription options.pp. 191
Session 6
Instruction fetch mechanisms for VLIW architectures with compressed encodingsFull-text access may be available. Sign in or learn about subscription options.pp. 201
Session 7
Tango: a hardware-based data prefetching technique for superscalar processorsFull-text access may be available. Sign in or learn about subscription options.pp. 214
Session 7
Exceeding the Dataflow Limit via Value PredictionFull-text access may be available. Sign in or learn about subscription options.pp. 226
Session 7
The performance potential of data dependence speculation and collapsingFull-text access may be available. Sign in or learn about subscription options.pp. 238
Session 8
Heuristics for Register-constrained Software PipeliningFull-text access may be available. Sign in or learn about subscription options.pp. 250
Session 8
Software Pipelining Loops with Conditional BranchesFull-text access may be available. Sign in or learn about subscription options.pp. 262
Session 8
Combining loop transformations considering caches and schedulingFull-text access may be available. Sign in or learn about subscription options.pp. 274
Session 9
Instruction Scheduling and Executable EditingFull-text access may be available. Sign in or learn about subscription options.pp. 288
Session 9
Instruction scheduling for the HP PA-8000Full-text access may be available. Sign in or learn about subscription options.pp. 298
Session 9
Meld Scheduling: Relaxing Scheduling Constraints across Region BoundariesFull-text access may be available. Sign in or learn about subscription options.pp. 308
Session 10
Custom--Fit Processors: Letting Applications Define ArchitecturesFull-text access may be available. Sign in or learn about subscription options.pp. 324
Session 10
Optimization for a Superscalar Out-of-Order MachineFull-text access may be available. Sign in or learn about subscription options.pp. 336
Session 10
Optimization of Machine Descriptions for Efficient UseFull-text access may be available. Sign in or learn about subscription options.pp. 349
Session 10
Author IndexFreely available from IEEE.pp. 359
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