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Proceedings of 30th Annual International Symposium on Microarchitecture

Dec. 1 1997 to Dec. 3 1997

Research Triangle Park, NC

ISSN: 1072-4451

ISBN: 0-8186-7977-8

Table of Contents

ForewordFreely available from IEEE.pp. viii
Conference CommitteeFreely available from IEEE.pp. ix
Program CommitteeFreely available from IEEE.pp. x
ReviewersFreely available from IEEE.pp. xi
Speaker BiographiesFull-text access may be available. Sign in or learn about subscription options.pp. xiii
Session 1: Instruction Fetch: Chair: Brad Calder, University of California, San Diego
The Bi-Mode Branch PredictoraFull-text access may be available. Sign in or learn about subscription options.pp. 4
Session 1: Instruction Fetch: Chair: Brad Calder, University of California, San Diego
Path-Based Next Trace PredictionFull-text access may be available. Sign in or learn about subscription options.pp. 14
Session 1: Instruction Fetch: Chair: Brad Calder, University of California, San Diego
Alternative Fetch and Issue Policies for the Trace Cache Fetch MechanismFull-text access may be available. Sign in or learn about subscription options.pp. 24
Session 1: Instruction Fetch: Chair: Brad Calder, University of California, San Diego
Reducing the Performance Impact of Instruction Cache Misses by Writing Instructions into the Reservation Stations Out-of-OrderFull-text access may be available. Sign in or learn about subscription options.pp. 34
Session 2: Data Cache Improvements: Chair: Jim Bondi, Texas Instruments
On High-Bandwidth Data Cache Design for Multi-Issue ProcessorsFull-text access may be available. Sign in or learn about subscription options.pp. 46
Session 2: Data Cache Improvements: Chair: Jim Bondi, Texas Instruments
Run-time Spatial Locality Detection and OptimizationFull-text access may be available. Sign in or learn about subscription options.pp. 57
Session 2: Data Cache Improvements: Chair: Jim Bondi, Texas Instruments
A Comparison of Data Prefetching on an Access Decoupled and Superscalar ArchitectureFull-text access may be available. Sign in or learn about subscription options.pp. 65
Session 2: Data Cache Improvements: Chair: Jim Bondi, Texas Instruments
The design and performance of a conflict-avoiding cacheFull-text access may be available. Sign in or learn about subscription options.pp. 71
Session 2: Data Cache Improvements: Chair: Jim Bondi, Texas Instruments
Prediction Caches for Superscalar ProcessorsFull-text access may be available. Sign in or learn about subscription options.pp. 81
Session 3: ILP Compiler Techniques I: Chair: Jim Dehnert, Silicon Graphics, Inc.
A framework for balancing control flow and predicationFull-text access may be available. Sign in or learn about subscription options.pp. 92
Session 3: ILP Compiler Techniques I: Chair: Jim Dehnert, Silicon Graphics, Inc.
Evaluation of scheduling techniques on a SPARC-based VLIW testbedFull-text access may be available. Sign in or learn about subscription options.pp. 104
Session 3: ILP Compiler Techniques I: Chair: Jim Dehnert, Silicon Graphics, Inc.
Tuning compiler optimizations for simultaneous multithreadingFull-text access may be available. Sign in or learn about subscription options.pp. 114
Session 3: ILP Compiler Techniques I: Chair: Jim Dehnert, Silicon Graphics, Inc.
Exploiting Dead Value InformationFull-text access may be available. Sign in or learn about subscription options.pp. 125
Session 4: Novel Microarchitectures: Chair: Ilan Spillinger, Intel
Trace ProcessorsFull-text access may be available. Sign in or learn about subscription options.pp. 138
Session 4: Novel Microarchitectures: Chair: Ilan Spillinger, Intel
The Multicluster Architecture: Reducing Cycle Time Through PartitioningFull-text access may be available. Sign in or learn about subscription options.pp. 149
Session 4: Novel Microarchitectures: Chair: Ilan Spillinger, Intel
Out-of-Order Vector ArchitecturesFull-text access may be available. Sign in or learn about subscription options.pp. 160
Session 4: Novel Microarchitectures: Chair: Ilan Spillinger, Intel
Initial Results on the Performance and Cost of Vector MicroprocessorsFull-text access may be available. Sign in or learn about subscription options.pp. 171
Session 5: Memory for Embedded Processors: Chair: Andrew Wolfe, Princeton University
The filter cache: an energy efficient memory structureFull-text access may be available. Sign in or learn about subscription options.pp. 184
Session 5: Memory for Embedded Processors: Chair: Andrew Wolfe, Princeton University
Improving Code Density Using Compression TechniquesFull-text access may be available. Sign in or learn about subscription options.pp. 194
Session 5: Memory for Embedded Processors: Chair: Andrew Wolfe, Princeton University
Procedure based program compressionFull-text access may be available. Sign in or learn about subscription options.pp. 204
Session 6: Load/Store Tuning: Chair: Dean Tullsen, University of California, San Diego
Improving the accuracy and performance of memory communication through renamingFull-text access may be available. Sign in or learn about subscription options.pp. 218
Session 6: Load/Store Tuning: Chair: Dean Tullsen, University of California, San Diego
Microarchitecture support for improving the performance of load target predictionFull-text access may be available. Sign in or learn about subscription options.pp. 228
Session 6: Load/Store Tuning: Chair: Dean Tullsen, University of California, San Diego
Streamlining inter-operation memory communication via data dependence predictionFull-text access may be available. Sign in or learn about subscription options.pp. 235
Session 7: Value Prediction: Chair: Nancy Warter-Perez, California State University, Los Angeles
The Predictability of Data ValuesFull-text access may be available. Sign in or learn about subscription options.pp. 248
Session 7: Value Prediction: Chair: Nancy Warter-Perez, California State University, Los Angeles
Value ProfilingFull-text access may be available. Sign in or learn about subscription options.pp. 259
Session 7: Value Prediction: Chair: Nancy Warter-Perez, California State University, Los Angeles
Can Program Profiling Support Value Prediction?Full-text access may be available. Sign in or learn about subscription options.pp. 270
Session 7: Value Prediction: Chair: Nancy Warter-Perez, California State University, Los Angeles
Highly Accurate Data Value Prediction using Hybrid PredictorsFull-text access may be available. Sign in or learn about subscription options.pp. 281
Session 8: Profiling and Benchmarking: Chair: Steve Beaty, Hewlett-Packard
ProfileMe: Hardware Support for Instruction-Level Profiling on Out-of-Order ProcessorsFull-text access may be available. Sign in or learn about subscription options.pp. 292
Session 8: Profiling and Benchmarking: Chair: Steve Beaty, Hewlett-Packard
Procedure Placement Using Temporal Ordering InformationFull-text access may be available. Sign in or learn about subscription options.pp. 303
Session 8: Profiling and Benchmarking: Chair: Steve Beaty, Hewlett-Packard
Predicting Data Cache Misses in Non-Numeric Applications Through Correlation ProfilingFull-text access may be available. Sign in or learn about subscription options.pp. 314
Session 8: Profiling and Benchmarking: Chair: Steve Beaty, Hewlett-Packard
Available parallelism in video applicationsFull-text access may be available. Sign in or learn about subscription options.pp. 321
Session 8: Profiling and Benchmarking: Chair: Steve Beaty, Hewlett-Packard
MediaBench: a tool for evaluating and synthesizing multimedia and communications systemsFull-text access may be available. Sign in or learn about subscription options.pp. 330
Session 9: ILP Compiler Techniques II: Chair: Scott Mahlke, Hewlett-Packard
Cache Sensitive Modulo SchedulingFull-text access may be available. Sign in or learn about subscription options.pp. 338
Session 9: ILP Compiler Techniques II: Chair: Scott Mahlke, Hewlett-Packard
Unroll-and-Jam Using Uniformly Generated SetsFull-text access may be available. Sign in or learn about subscription options.pp. 349
Session 9: ILP Compiler Techniques II: Chair: Scott Mahlke, Hewlett-Packard
Resource-sensitive profile-directed data flow analysis for code optimizationFull-text access may be available. Sign in or learn about subscription options.pp. 358
Session 9: ILP Compiler Techniques II: Chair: Scott Mahlke, Hewlett-Packard
Author IndexFreely available from IEEE.pp. 369
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