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37th International Symposium on Microarchitecture (MICRO-37'04)

Dec. 4 2004 to Dec. 8 2004

Portland,Oregon

ISSN: 1072-4451

ISBN: 0-7695-2126-6

Table of Contents

Message from the General and Program ChairsFreely available from IEEE.pp. ix
list-reviewerFreely available from IEEE.pp. xii,xiii
Keynote 1
Microarchitecture and Design Challenges for Gigascale IntegrationFreely available from IEEE.pp. 3-3
by S. Borkar
Session 1: Instruction Collapsing
Dynamic Strands: Collapsing Speculative Dependence Chains for Reducing Pipeline CommunicationFull-text access may be available. Sign in or learn about subscription options.pp. 7-17
by Peter G. Sassone, D. Scott Wills
Session 1: Instruction Collapsing
Dataflow Mini-Graphs: Amplifying Superscalar Capacity and BandwidthFull-text access may be available. Sign in or learn about subscription options.pp. 18-29
by Anne Bracy, Prashant Prahlad, Amir Roth
Session 1: Instruction Collapsing
Application-Specific Processing on a General-Purpose Core via Transparent Instruction Set CustomizationFull-text access may be available. Sign in or learn about subscription options.pp. 30-40
by Nathan Clark, Manjunath Kudlur, Hyunchul Park, Scott Mahlke, Kriszti? Flautner
Session 2: Performance Evaluation
MicroLib: A Case for the Quantitative Comparison of Micro-Architecture MechanismsFull-text access may be available. Sign in or learn about subscription options.pp. 43-54
by Daniel Gracia P?rez, Gilles Mouchard, Olivier Temam
Session 2: Performance Evaluation
Automatic Synthesis of High-Speed Processor SimulatorsFull-text access may be available. Sign in or learn about subscription options.pp. 55-66
by Martin Burtscher, Ilya Ganusov
Session 2: Performance Evaluation
Thermal Modeling, Characterization and Management of On-Chip NetworksFull-text access may be available. Sign in or learn about subscription options.pp. 67-78
by Li Shang, Li-Shiuan Peh, Amit Kumar, Niraj K. Jha
Session 3: Trace Analysis
Pinpointing Representative Portions of Large Intel? Itanium? Programs with Dynamic InstrumentationFull-text access may be available. Sign in or learn about subscription options.pp. 81-92
by Harish Patil, Robert Cohn, Mark Charney, Rajiv Kapoor, Andrew Sun, Anand Karunanidhi
Session 3: Trace Analysis
The Fuzzy Correlation between Code and Performance PredictabilityFull-text access may be available. Sign in or learn about subscription options.pp. 93-104
by Murali Annavaram, Ryan Rakvic, Marzia Polito, Jean-Yves Bouguet, Richard Hankins, Bob Davies
Session 3: Trace Analysis
Whole Execution TracesFull-text access may be available. Sign in or learn about subscription options.pp. 105-116
by Xiangyu Zhang, Rajiv Gupta
Session 4: Control Flow
Wrong Path Events: Exploiting Unusual and Illegal Program Behavior for Early Misprediction Detection and RecoveryFull-text access may be available. Sign in or learn about subscription options.pp. 119-128
by David N. Armstrong, Hyesoon Kim, Onur Mutlu, Yale N. Patt
Control Flow Optimization Via Dynamic Reconvergence PredictionFull-text access may be available. Sign in or learn about subscription options.pp. 129-140
by J.D. Collins, D.M. Tullsen, Hong Wang
Keynote 2
Single-Chip Multiprocessors: The Next Wave of Computer Architecture InnovationFreely available from IEEE.pp. 143-143
by G. Sohi
Session 5: Adaptive Microarchitectures
A Case for Clumsy Packet ProcessorsFull-text access may be available. Sign in or learn about subscription options.pp. 147-156
by Arindam Mallik, Gokhan Memik
Session 5: Adaptive Microarchitectures
Dynamically Trading Frequency for Complexity in a GALS MicroprocessorFull-text access may be available. Sign in or learn about subscription options.pp. 157-168
by Steven Dropsho, Greg Semeraro, David H. Albonesi, Grigorios Magklis, Michael L. Scott
Session 6: Multithreaded/Multicore Processors
Dynamically Controlled Resource Allocation in SMT ProcessorsFull-text access may be available. Sign in or learn about subscription options.pp. 171-182
by Francisco J. Cazorla, Alex Ramirez, Mateo Valero, Enrique Fern?ndez
Session 6: Multithreaded/Multicore Processors
Balanced Multithreading: Increasing Throughput via a Low Cost Multithreading HierarchyFull-text access may be available. Sign in or learn about subscription options.pp. 183-194
by Eric Tune, Rakesh Kumar, Dean M. Tullsen, Brad Calder
Session 6: Multithreaded/Multicore Processors
Conjoined-Core Chip MultiprocessingFull-text access may be available. Sign in or learn about subscription options.pp. 195-206
by Rakesh Kumar, Norman P. Jouppi, Dean M. Tullsen
Session 7: Security
Hardware and Binary Modification Support for Code Pointer Protection From Buffer OverflowFull-text access may be available. Sign in or learn about subscription options.pp. 209-220
by Nathan Tuck, Brad Calder, George Varghese
Session 7: Security
Minos: Control Data Attack Prevention Orthogonal to Memory ModelFull-text access may be available. Sign in or learn about subscription options.pp. 221-232
by Jedidiah R. Crandall, Frederic T. Chong
Session 7: Security
A Hardware-Software Platform for Intrusion PreventionFull-text access may be available. Sign in or learn about subscription options.pp. 233-242
by Milenko Drinic, Darko Kirovski
Session 7: Security
RIFLE: An Architectural Framework for User-Centric Information-Flow SecurityFull-text access may be available. Sign in or learn about subscription options.pp. 243-254
by Neil Vachharajani, Matthew J. Bridges, Jonathan Chang, Ram Rangan, Guilherme Ottoni, Jason A. Blome, George A. Reis, Manish Vachharajani, David I. August
Session 8: Reliability
Efficient Resource Sharing in Concurrent Error Detecting Superscalar MicroarchitecturesFull-text access may be available. Sign in or learn about subscription options.pp. 257-268
by Jared C. Smolens, Jangwoo Kim, James C. Hoe, Babak Falsafi
Session 8: Reliability
AccMon: Automatically Detecting Memory-Related Bugs via Program Counter-Based InvariantsFull-text access may be available. Sign in or learn about subscription options.pp. 269-280
by Pin Zhou, Wei Liu, Long Fei, Shan Lu, Feng Qin, Yuanyuan Zhou, Samuel Midkiff, Josep Torrellas
Session 9: Code Generation and Optimization
Optimal Superblock Scheduling Using EnumerationFull-text access may be available. Sign in or learn about subscription options.pp. 283-293
by Ghassan Shobaki, Kent Wilken
Session 9: Code Generation and Optimization
Compiler Optimizations for Transaction Processing Workloads on Itanium? Linux SystemsFull-text access may be available. Sign in or learn about subscription options.pp. 294-303
by Gerolf Hoflehner, Knud Kirkegaard, Rod Skinner, Daniel Lavery, Yong-fong Lee, Wei Li
Session 9: Code Generation and Optimization
Register Packing: Exploiting Narrow-Width Operands for Reducing Register File PressureFull-text access may be available. Sign in or learn about subscription options.pp. 304-315
by Oguz Ergin, Deniz Balkan, Kanad Ghose, Dmitry Ponomarev
Session 10: Caches and Memory
Managing Wire Delay in Large Chip-Multiprocessor CachesFull-text access may be available. Sign in or learn about subscription options.pp. 319-330
by Bradford M. Beckmann, David A. Wood
Session 10: Caches and Memory
Cache Refill/Access Decoupling for Vector MachinesFull-text access may be available. Sign in or learn about subscription options.pp. 331-342
by Christopher Batten, Ronny Krashinsky, Steve Gerding, Krste Asanovic
Session 10: Caches and Memory
Adaptive History-Based Memory SchedulersFull-text access may be available. Sign in or learn about subscription options.pp. 343-354
by Ibrahim Hur, Calvin Lin
Session 10: Caches and Memory
Memory Controller Optimizations for Web ServersFull-text access may be available. Sign in or learn about subscription options.pp. 355-366
by Scott Rixner
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