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40th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO 2007)

Dec. 1 2007 to Dec. 5 2007

Chicago, IL

Table of Contents

Session 1: Technology Issues
Optimizing NUCA Organizations and Wiring Alternatives for Large Caches with CACTI 6.0Full-text access may be available. Sign in or learn about subscription options.pp. 3-14
by R. Balasubramonian, N. Muralimanohar, N. Jouppi
Introduction
Message from the General ChairsFreely available from IEEE.pp. viii
Introduction
list-reviewerFreely available from IEEE.pp. xi
Introduction
Message from the Program ChairsFreely available from IEEE.pp. ix
40th Annual IEEE/ACM International Symposium on Microarchitecture - Title pageFreely available from IEEE.
40th Annual IEEE/ACM International Symposium on Microarchitecture - CopyrightFreely available from IEEE.
40th Annual IEEE/ACM International Symposium on Microarchitecture - Table of contentsFreely available from IEEE.
Introduction
Organizing CommitteeFreely available from IEEE.pp. x
Session 1: Technology Issues
Process Variation Tolerant 3T1D-Based Cache ArchitecturesFull-text access may be available. Sign in or learn about subscription options.pp. 15-26
by Xiaoyao Liang, Ramon Canal, Gu-Yeon Wei, David Brooks
Session 1: Technology Issues
Mitigating Parameter Variation with Dynamic Fine-Grain Body BiasingFull-text access may be available. Sign in or learn about subscription options.pp. 27-42
by Radu Teodorescu, Jun Nakano, Abhishek Tiwari, Josep Torrellas
Session 2A: Instruction Scheduling
Optimal versus Heuristic Global Code SchedulingFull-text access may be available. Sign in or learn about subscription options.pp. 43-55
by Sebastian Winkel
Session 2A: Instruction Scheduling
Global Multi-Threaded Instruction SchedulingFull-text access may be available. Sign in or learn about subscription options.pp. 56-68
by Guilherme Ottoni, David August
Session 2A: Instruction Scheduling
Revisiting the Sequential Programming Model for Multi-CoreFull-text access may be available. Sign in or learn about subscription options.pp. 69-84
by Matthew Bridges, Neil Vachharajani, Yun Zhang, Thomas Jablin, David August
Session 2B: Wear-Out Aware Architectures
Penelope: The NBTI-Aware ProcessorFull-text access may be available. Sign in or learn about subscription options.pp. 85-96
by Jaume Abella, Xavier Vera, Antonio Gonz?lez
Session 2B: Wear-Out Aware Architectures
Software-Based Online Detection of Hardware Defects Mechanisms, Architectural Support, and EvaluationFull-text access may be available. Sign in or learn about subscription options.pp. 97-108
by Kypros Constantinides, Onur Mutlu, Todd Austin, Valeria Bertacco
Session 2B: Wear-Out Aware Architectures
Self-calibrating Online Wearout DetectionFull-text access may be available. Sign in or learn about subscription options.pp. 109-122
by Jason Blome, Shuguang Feng, Shantanu Gupta, Scott Mahlke
Session 3A: Memory
Implementing Signatures for Transactional MemoryFull-text access may be available. Sign in or learn about subscription options.pp. 123-133
by Daniel Sanchez, Luke Yen, Mark D. Hill, Karthikeyan Sankaralingam
Session 3A: Memory
Smart Refresh: An Enhanced Memory Controller Design for Reducing Energy in Conventional and 3D Die-Stacked DRAMsFull-text access may be available. Sign in or learn about subscription options.pp. 134-145
by Mrinmoy Ghosh, Hsien-Hsin S. Lee
Session 3A: Memory
Stall-Time Fair Memory Access Scheduling for Chip MultiprocessorsFull-text access may be available. Sign in or learn about subscription options.pp. 146-160
by Onur Mutlu, Thomas Moscibroda
Session 3B: Networking and Security
Impact of Cache Coherence Protocols on the Processing of Network TrafficFull-text access may be available. Sign in or learn about subscription options.pp. 161-171
by Amit Kumar, Ram Huggahalli
Session 3B: Networking and Security
Flattened Butterfly Topology for On-Chip NetworksFull-text access may be available. Sign in or learn about subscription options.pp. 172-182
by John Kim, James Balfour, William Dally
Session 3B: Networking and Security
Using Address Independent Seed Encryption and Bonsai Merkle Trees to Make Secure Processors OS- and Performance-FriendlyFull-text access may be available. Sign in or learn about subscription options.pp. 183-196
by Brian Rogers, Siddhartha Chhabra, Milos Prvulovic, Yan Solihin
Session 4A: Reliability
Multi-bit Error Tolerant Caches Using Two-Dimensional Error CodingFull-text access may be available. Sign in or learn about subscription options.pp. 197-209
by Jangwoo Kim, Nikos Hardavellas, Ken Mai, Babak Falsafi, James Hoe
Session 4A: Reliability
Argus: Low-Cost, Comprehensive Error Detection in Simple CoresFull-text access may be available. Sign in or learn about subscription options.pp. 210-222
by Albert Meixner, Michael E. Bauer, Daniel Sorin
Session 4A: Reliability
Leveraging 3D Technology for Improved ReliabilityFull-text access may be available. Sign in or learn about subscription options.pp. 223-235
by Niti Madan, Rajeev Balasubramonian
Session 4A: Reliability
Effective Optimistic-Checker Tandem Core Design through Architectural PruningFull-text access may be available. Sign in or learn about subscription options.pp. 236-248
by Francisco Mesa-Mart?nez, Jose Renau
Session 4B: Simulation/Workload Analysis
FPGA-Accelerated Simulation Technologies (FAST): Fast, Full-System, Cycle-Accurate SimulatorsFull-text access may be available. Sign in or learn about subscription options.pp. 249-261
by Derek Chiou, Dam Sunwoo, Joonsoo Kim, Nikhil A. Patil, William Reinhart, Darrel Eric Johnson, Jebediah Keefe, Hari Angepat
Session 4B: Simulation/Workload Analysis
Microarchitectural Design Space Exploration Using an Architecture-Centric ApproachFull-text access may be available. Sign in or learn about subscription options.pp. 262-271
by Christophe Dubach, Timothy Jones, Michael O?Boyle
Session 4B: Simulation/Workload Analysis
Informed Microarchitecture Design Space Exploration Using Workload DynamicsFull-text access may be available. Sign in or learn about subscription options.pp. 274-285
by Chang-Burm Cho, Wangyuan Zhang, Tao Li
Session 4B: Simulation/Workload Analysis
Time Interpolation: So Many Metrics, So Few RegistersFull-text access may be available. Sign in or learn about subscription options.pp. 286-300
by Todd Mytkowicz, Peter F. Sweeney, Matthias Hauswirth, Amer Diwan
Emulating Optimal Replacement with a Shepherd CacheFull-text access may be available. Sign in or learn about subscription options.pp. 445-454
by Kaushik Rajan, Govindarajan Ramaswamy
Session 5: Prefetching and Snooping
Low-Cost Epoch-Based Correlation Prefetching for Commercial ApplicationsFull-text access may be available. Sign in or learn about subscription options.pp. 301-313
by Yuan Chou
Session 5: Prefetching and Snooping
A Framework for Coarse-Grain Optimizations in the On-Chip Memory HierarchyFull-text access may be available. Sign in or learn about subscription options.pp. 314-327
by Jason Zebchuk, Elham Safi, Andreas Moshovos
Session 5: Prefetching and Snooping
Uncorq: Unconstrained Snoop Request Delivery in Embedded-Ring MultiprocessorsFull-text access may be available. Sign in or learn about subscription options.pp. 327-342
by Karin Strauss, Xiaowei Shen, Josep Torrellas
Session 6: Parallelism and QoS in CMPs
A Framework for Providing Quality of Service in Chip Multi-ProcessorsFull-text access may be available. Sign in or learn about subscription options.pp. 343-355
by Fei Guo, Yan Solihin, Li Zhao, Ravishankar Iyer
Session 6: Parallelism and QoS in CMPs
A Practical Approach to Exploiting Coarse-Grained Pipeline Parallelism in C ProgramsFull-text access may be available. Sign in or learn about subscription options.pp. 356-369
by William Thies, Vikram Chandrasekhar, Saman Amarasinghe
Session 6: Parallelism and QoS in CMPs
Data Access Partitioning for Fine-grain Parallelism on Multicore ArchitecturesFull-text access may be available. Sign in or learn about subscription options.pp. 369-380
by Michael Chu, Rajiv Ravindran, Scott Mahlke
Session 7: Parallel Architectures
Composable Lightweight ProcessorsFull-text access may be available. Sign in or learn about subscription options.pp. 381-394
by Changkyu Kim, Simha Sethumadhavan, M.S. Govindan, Nitya Ranganathan, Divya Gulati, Doug Burger, Stephen W. Keckler
Session 7: Parallel Architectures
The Art of Deception: Adaptive Precision Reduction for Area Efficient Physics AccelerationFull-text access may be available. Sign in or learn about subscription options.pp. 394-406
by Thomas Yeh, Petros Faloutsos, Milos Ercegovac, Sanjay Patel, Glenn Reinman
Session 7: Parallel Architectures
Dynamic Warp Formation and Scheduling for Efficient GPU Control FlowFull-text access may be available. Sign in or learn about subscription options.pp. 407-420
by Wilson W.L. Fung, Ivan Sham, George Yuan, Tor M. Aamodt
Session 8: Cache Replacement Policies
Scavenger: A New Last Level Cache Architecture with Global Block PriorityFull-text access may be available. Sign in or learn about subscription options.pp. 421-432
by Arkaprava Basu, Nevin Kirman, Meyrem Kirman, Mainak Chaudhuri, Jos? Mart?nez
Session 8: Cache Replacement Policies
Guaranteeing Hits to Improve the Efficiency of a Small Instruction CacheFull-text access may be available. Sign in or learn about subscription options.pp. 433-444
by Stephen Hines, David Whalley, Gary Tyson
Author Index
Author IndexFreely available from IEEE.pp. 455
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