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2012 45th Annual IEEE/ACM International Symposium on Microarchitecture

Dec. 1 2012 to Dec. 5 2012

Vancouver, BC, Canada Canada

ISSN: 1072-4451

ISBN: 978-1-4673-4819-5

Table of Contents

Papers
[Title page i]Freely available from IEEE.pp. i
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[Title page iii]Freely available from IEEE.pp. iii
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[Copyright notice]Freely available from IEEE.pp. iv
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Table of contentsFreely available from IEEE.pp. v-viii
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Message from the General ChairFreely available from IEEE.pp. ix
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Message from the Program ChairFreely available from IEEE.pp. x-xii
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Organizing CommitteeFreely available from IEEE.pp. xiii
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Program CommitteeFreely available from IEEE.pp. xiv
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External Review CommitteeFreely available from IEEE.pp. xv-xvi
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ReviewersFreely available from IEEE.pp. xvii-xix
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FPB: Fine-grained Power Budgeting to Improve Write Throughput of Multi-level Cell Phase Change MemoryFull-text access may be available. Sign in or learn about subscription options.pp. 1-12
by Lei Jiang, Youtao Zhang, Bruce R. Childers, Jun Yang
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Leveraging Heterogeneity in DRAM Main Memories to Accelerate Critical Word AccessFull-text access may be available. Sign in or learn about subscription options.pp. 13-24
by Niladrish Chatterjee, Manjunath Shevgoor, Rajeev Balasubramonian, Al Davis, Zhen Fang, Ramesh Illikkal, Ravi Iyer
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Transactional Memory Architecture and Implementation for IBM System ZFull-text access may be available. Sign in or learn about subscription options.pp. 25-36
by Christian Jacobi, Timothy Slegel, Dan Greiner
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Warped-DMR: Light-weight Error Detection for GPGPUFull-text access may be available. Sign in or learn about subscription options.pp. 37-47
by Hyeran Jeon, Murali Annavaram
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The Performance Vulnerability of Architectural and Non-architectural Arrays to Permanent FaultsFull-text access may be available. Sign in or learn about subscription options.pp. 48-59
by Damien Hardy, Isidoros Sideris, Nikolas Ladas, Yiannakis Sazeides
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NoCAlert: An On-Line and Real-Time Fault Detection Mechanism for Network-on-Chip ArchitecturesFull-text access may be available. Sign in or learn about subscription options.pp. 60-71
by Andreas Prodromou, Andreas Panteli, Chrysostomos Nicopoulos, Yiannakis Sazeides
Cache-Conscious Wavefront SchedulingFull-text access may be available. Sign in or learn about subscription options.pp. 72-83
by Timothy G. Rogers, Mike O'Connor, Tor M. Aamodt
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Libra: Tailoring SIMD Execution Using Heterogeneous Hardware and Dynamic ConfigurabilityFull-text access may be available. Sign in or learn about subscription options.pp. 84-95
by Yongjun Park, Jason Jong Kyu Park, Hyunchul Park, Scott Mahlke
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Unifying Primary Cache, Scratch, and Register File Memories in a Throughput ProcessorFull-text access may be available. Sign in or learn about subscription options.pp. 96-106
by Mark Gebhart, Stephen W. Keckler, Brucek Khailany, Ronny Krashinsky, William J. Dally
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Kernel Weaver: Automatically Fusing Database Primitives for Efficient GPU ComputationFull-text access may be available. Sign in or learn about subscription options.pp. 107-118
by Haicheng Wu, Gregory Diamos, Srihari Cadambi, Sudhakar Yalamanchili
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KnightShift: Scaling the Energy Proportionality Wall through Server-Level HeterogeneityFull-text access may be available. Sign in or learn about subscription options.pp. 119-130
by Daniel Wong, Murali Annavaram
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Rethinking DRAM Power Modes for Energy ProportionalityFull-text access may be available. Sign in or learn about subscription options.pp. 131-142
by Krishna T. Malladi, Ian Shaeffer, Liji Gopalakrishnan, David Lo, Benjamin C. Lee, Mark Horowitz
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CoScale: Coordinating CPU and Memory System DVFS in Server SystemsFull-text access may be available. Sign in or learn about subscription options.pp. 143-154
by Qingyuan Deng, David Meisner, Abhishek Bhattacharjee, Thomas F. Wenisch, Ricardo Bianchini
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Predicting Performance Impact of DVFS for Realistic Memory SystemsFull-text access may be available. Sign in or learn about subscription options.pp. 155-165
by Rustam Miftakhutdinov, Eiman Ebrahimi, Yale N. Patt
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Vector Extensions for Decision Support DBMS AccelerationFull-text access may be available. Sign in or learn about subscription options.pp. 166-176
by Timothy Hayes, Oscar Palomar, Osman Unsal, Adrian Cristal, Mateo Valero
NOC-Out: Microarchitecting a Scale-Out ProcessorFull-text access may be available. Sign in or learn about subscription options.pp. 177-187
by Pejman Lotfi-Kamran, Boris Grot, Babak Falsafi
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SLICC: Self-Assembly of Instruction Cache Collectives for OLTP WorkloadsFull-text access may be available. Sign in or learn about subscription options.pp. 188-198
by Islam Atta, Pinar Tozun, Anastasia Ailamaki, Andreas Moshovos
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Systematic Energy Characterization of CMP/SMT Processor Systems via Automated Micro-BenchmarksFull-text access may be available. Sign in or learn about subscription options.pp. 199-211
by Ramon Bertran, Alper Buyuktosunoglu, Meeta S. Gupta, Marc Gonzalez, Pradip Bose
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AUDIT: Stress Testing the Automatic WayFull-text access may be available. Sign in or learn about subscription options.pp. 212-223
by Youngtaek Kim, Lizy Kurian John, Sanjay Pant, Srilatha Manne, Michael Schulte, W. Lloyd Bircher, Madhu S. Sibi Govindan
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Accurate Fine-Grained Processor Power ProxiesFull-text access may be available. Sign in or learn about subscription options.pp. 224-234
by Wei Huang, Charles Lefurgy, William Kuk, Alper Buyuktosunoglu, Michael Floyd, Karthick Rajamani, Malcolm Allen-Ware, Bishop Brock
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Fundamental Latency Trade-off in Architecting DRAM Caches: Outperforming Impractical SRAM-Tags with a Simple and Practical DesignFull-text access may be available. Sign in or learn about subscription options.pp. 235-246
by Moinuddin K. Qureshi, Gabe H. Loh
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A Mostly-Clean DRAM Cache for Effective Hit Speculation and Self-Balancing DispatchFull-text access may be available. Sign in or learn about subscription options.pp. 247-257
by Jaewoong Sim, Gabriel H. Loh, Hyesoon Kim, Mike OConnor, Mithuna Thottethodi
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CoLT: Coalesced Large-Reach TLBsFull-text access may be available. Sign in or learn about subscription options.pp. 258-269
by Binh Pham, Viswanathan Vaidyanathan, Aamer Jaleel, Abhishek Bhattacharjee
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NoRD: Node-Router Decoupling for Effective Power-gating of On-Chip RoutersFull-text access may be available. Sign in or learn about subscription options.pp. 270-281
by Lizhong Chen, Timothy M. Pinkston
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Dynamic Reconfiguration of 3D Photonic Networks-on-Chip for Maximizing Performance and Improving Fault ToleranceFull-text access may be available. Sign in or learn about subscription options.pp. 282-293
by Randy Morris, Avinash Karanth Kodi, Ahmed Louri
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Addressing End-to-End Memory Access Latency in NoC-Based MulticoresFull-text access may be available. Sign in or learn about subscription options.pp. 294-304
by Akbar Sharifi, Emre Kultursay, Mahmut Kandemir, Chita R. Das
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MorphCore: An Energy-Efficient Microarchitecture for High Performance ILP and High Throughput TLPFull-text access may be available. Sign in or learn about subscription options.pp. 305-316
by Khubaib, M. Aater Suleman, Milad Hashemi, Chris Wilkerson, Yale N. Patt
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Composite Cores: Pushing Heterogeneity Into a CoreFull-text access may be available. Sign in or learn about subscription options.pp. 317-328
by Andrew Lukefahr, Shruti Padmanabha, Reetuparna Das, Faissal M. Sleiman, Ronald Dreslinski, Thomas F. Wenisch, Scott Mahlke
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Control-Flow DecouplingFull-text access may be available. Sign in or learn about subscription options.pp. 329-340
by Rami Sheikh, James Tuck, Eric Rotenberg
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Spatiotemporal Coherence TrackingFull-text access may be available. Sign in or learn about subscription options.pp. 341-350
by Mohammad Alisafaee
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Predicting Coherence Communication by Tracking Synchronization Points at Run TimeFull-text access may be available. Sign in or learn about subscription options.pp. 351-362
by Socrates Demetriades, Sangyeun Cho
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Vulcan: Hardware Support for Detecting Sequential Consistency Violations DynamicallyFull-text access may be available. Sign in or learn about subscription options.pp. 363-375
by Abdullah Muzahid, Shanxiang Qi, Josep Torrellas
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Amoeba-Cache: Adaptive Blocks for Eliminating Waste in the Memory HierarchyFull-text access may be available. Sign in or learn about subscription options.pp. 376-388
by Snehasish Kumar, Hongzhou Zhao, Arrvindh Shriraman, Eric Matthews, Sandhya Dwarkadas, Lesley Shannon
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Improving Cache Management Policies Using Dynamic Reuse DistancesFull-text access may be available. Sign in or learn about subscription options.pp. 389-400
by Nam Duong, Dali Zhao, Taesu Kim, Rosario Cammarota, Mateo Valero, Alexander V. Veidenbaum
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Kernel Partitioning of Streaming Applications: A Statistical Approach to an NP-complete ProblemFull-text access may be available. Sign in or learn about subscription options.pp. 401-412
by Petar Radojkovic, Paul M. Carpenter, Miquel Moreto, Alex Ramirez, Francisco J. Cazorla
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Inferred Models for Dynamic and Sparse Hardware-Software SpacesFull-text access may be available. Sign in or learn about subscription options.pp. 413-424
by Weidan Wu, Benjamin C. Lee
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SMARQ: Software-Managed Alias Register Queue for Dynamic OptimizationsFull-text access may be available. Sign in or learn about subscription options.pp. 425-436
by Cheng Wang, Youfeng Wu, Hongbo Rong, Hyunchul Park
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Profiling Data-Dependence to Assist Parallelization: Framework, Scope, and OptimizationFull-text access may be available. Sign in or learn about subscription options.pp. 437-448
by Alain Ketterlin, Philippe Clauss
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Neural Acceleration for General-Purpose Approximate ProgramsFull-text access may be available. Sign in or learn about subscription options.pp. 449-460
by Hadi Esmaeilzadeh, Adrian Sampson, Luis Ceze, Doug Burger
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Designing a Programmable Wire-Speed Regular-Expression Matching AcceleratorFull-text access may be available. Sign in or learn about subscription options.pp. 461-472
by Jan Van Lunteren, Christoph Hagleitner, Timothy Heil, Giora Biran, Uzi Shvadron, Kubilay Atasu
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Author indexFreely available from IEEE.pp. 473-474
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[Publisher's information]Freely available from IEEE.pp. 476
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