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2014 47th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO)

Dec. 13 2014 to Dec. 17 2014

Cambridge, United Kingdom

Table of Contents

Title Page iFreely available from IEEE.pp. i-i
Title Page iiiFreely available from IEEE.pp. iii-iii
Copyright PageFreely available from IEEE.pp. iv-iv
Table of ContentsFreely available from IEEE.pp. v-ix
Message from the General ChairFreely available from IEEE.pp. x-x
Message from the Program Co-ChairsFreely available from IEEE.pp. xi-xii
Organizing CommitteeFreely available from IEEE.pp. xiii-xiii
Program CommitteeFreely available from IEEE.pp. xiv-xv
External Reviewer CommitteeFreely available from IEEE.pp. xvi-xviii
External ReviewersFreely available from IEEE.pp. xix-xix
Keynote AbstractsFreely available from IEEE.pp. xx-xxii
CAMEO: A Two-Level Memory Organization with Capacity of Main Memory and Flexibility of Hardware-Managed CacheFull-text access may be available. Sign in or learn about subscription options.pp. 1-12
by Chia Chen Chou, Aamer Jaleel, Moinuddin K. Qureshi
Transparent Hardware Management of Stacked DRAM as Part of MemoryFull-text access may be available. Sign in or learn about subscription options.pp. 13-24
by Jaewoong Sim, Alaa R. Alameldeen, Zeshan Chishti, Chris Wilkerson, Hyesoon Kim
Unison Cache: A Scalable and Effective Die-Stacked DRAM CacheFull-text access may be available. Sign in or learn about subscription options.pp. 25-37
by Djordje Jevdjic, Gabriel H. Loh, Cansu Kaynak, Babak Falsafi
Bi-Modal DRAM Cache: Improving Hit Rate, Hit Latency and BandwidthFull-text access may be available. Sign in or learn about subscription options.pp. 38-50
by Nagendra Gulur, Mahesh Mehendale, R. Manikantan, R. Govindarajan
Citadel: Efficiently Protecting Stacked Memory from Large Granularity FailuresFull-text access may be available. Sign in or learn about subscription options.pp. 51-62
by Prashant J. Nair, David A. Roberts, Moinuddin K. Qureshi
Locality-Aware Mapping of Nested Parallel Patterns on GPUsFull-text access may be available. Sign in or learn about subscription options.pp. 63-74
by Hyoukjoong Lee, Kevin J. Brown, Arvind K. Sujeeth, Tiark Rompf, Kunle Olukotun
Accelerating Irregular Algorithms on GPGPUs Using Fine-Grain Hardware WorklistsFull-text access may be available. Sign in or learn about subscription options.pp. 75-87
by Ji Yun Kim, Christopher Batten
PORPLE: An Extensible Optimizer for Portable Data Placement on GPUFull-text access may be available. Sign in or learn about subscription options.pp. 88-100
by Guoyang Chen, Bo Wu, Dong Li, Xipeng Shen
Exploring the Design Space of SPMD Divergence Management on Data-Parallel ArchitecturesFull-text access may be available. Sign in or learn about subscription options.pp. 101-113
by Yunsup Lee, Vinod Grover, Ronny Krashinsky, Mark Stephenson, Stephen W. Keckler, Krste Asanovic
Managing GPU Concurrency in Heterogeneous ArchitecturesFull-text access may be available. Sign in or learn about subscription options.pp. 114-126
by Onur Kayiran, Nachiappan Chidambaram Nachiappan, Adwait Jog, Rachata Ausavarungnirun, Mahmut T. Kandemir, Gabriel H. Loh, Onur Mutlu, Chita R. Das
Load Value ApproximationFull-text access may be available. Sign in or learn about subscription options.pp. 127-139
by Joshua San Miguel, Mario Badr, Natalie Enright Jerger
Arbitrary Modulus IndexingFull-text access may be available. Sign in or learn about subscription options.pp. 140-152
by Jeffrey R. Diamond, Donald S. Fussell, Stephen W. Keckler
FIRM: Fair and High-Performance Memory Control for Persistent Memory SystemsFull-text access may be available. Sign in or learn about subscription options.pp. 153-165
by Jishen Zhao, Onur Mutlu, Yuan Xie
Short-Circuiting Memory Traffic in Handheld PlatformsFull-text access may be available. Sign in or learn about subscription options.pp. 166-177
by Praveen Yedlapalli, Nachiappan Chidambaram Nachiappan, Niranjan Soundararajan, Anand Sivasubramaniam, Mahmut T. Kandemir, Chita R. Das
Efficient Memory Virtualization: Reducing Dimensionality of Nested Page WalksFull-text access may be available. Sign in or learn about subscription options.pp. 178-189
by Jayneel Gandhi, Arkaprava Basu, Mark D. Hill, Michael M. Swift
Iso-X: A Flexible Architecture for Hardware-Managed Isolated ExecutionFull-text access may be available. Sign in or learn about subscription options.pp. 190-202
by Dmitry Evtyushkin, Jesse Elwell, Meltem Ozsoy, Dmitry Ponomarev, Nael Abu Ghazaleh, Ryan Riley
Random Fill Cache ArchitectureFull-text access may be available. Sign in or learn about subscription options.pp. 203-215
by Fangfei Liu, Ruby B. Lee
CC-Hunter: Uncovering Covert Timing Channels on Shared Processor HardwareFull-text access may be available. Sign in or learn about subscription options.pp. 216-228
by Jie Chen, Guru Venkataramani
Continuous, Low Overhead, Run-Time Validation of Program ExecutionsFull-text access may be available. Sign in or learn about subscription options.pp. 229-241
by Erdem Aktas, Furat Afram, Kanad Ghose
A Practical Methodology for Measuring the Side-Channel Signal Available to the Attacker for Instruction-Level EventsFull-text access may be available. Sign in or learn about subscription options.pp. 242-254
by Robert Callan, Alenka Zajic, Milos Prvulovic
RpStacks: Fast and Accurate Processor Design Space Exploration Using Representative Stall-Event StacksFull-text access may be available. Sign in or learn about subscription options.pp. 255-267
by Jaewon Lee, Hanhwi Jang, Jangwoo Kim
GPUMech: GPU Performance Modeling Technique Based on Interval AnalysisFull-text access may be available. Sign in or learn about subscription options.pp. 268-279
by Jen-Cheng Huang, Joo Hwan Lee, Hyesoon Kim, Hsien-Hsin S. Lee
PyMTL: A Unified Framework for Vertically Integrated Computer Architecture ResearchFull-text access may be available. Sign in or learn about subscription options.pp. 280-292
by Derek Lockhart, Gary Zibrat, Christopher Batten
Calculating Architectural Vulnerability Factors for Spatial Multi-Bit Transient FaultsFull-text access may be available. Sign in or learn about subscription options.pp. 293-305
by Mark Wilkening, Vilas Sridharan, Si Li, Fritz Previlon, Sudhanva Gurumurthi, David R. Kaeli
Using ECC Feedback to Guide Voltage Speculation in Low-Voltage ProcessorsFull-text access may be available. Sign in or learn about subscription options.pp. 306-318
by Anys Bacha, Radu Teodorescu
Harnessing Soft Computations for Low-Budget Fault ToleranceFull-text access may be available. Sign in or learn about subscription options.pp. 319-330
by Daya Shanker Khudia, Scott Mahlke
Skewed Compressed CachesFull-text access may be available. Sign in or learn about subscription options.pp. 331-342
by Somayeh Sardashti, Andre Seznec, David A. Wood
Adaptive Cache Management for Energy-Efficient GPU ComputingFull-text access may be available. Sign in or learn about subscription options.pp. 343-355
by Xuhao Chen, Li-Wen Chang, Christopher I. Rodrigues, Jie Lv, Zhiying Wang, Wen-Mei Hwu
Futility Scaling: High-Associativity Cache PartitioningFull-text access may be available. Sign in or learn about subscription options.pp. 356-367
by Ruisheng Wang, Lizhong Chen
Voltage Noise in Multi-Core Processors: Empirical Characterization and Optimization OpportunitiesFull-text access may be available. Sign in or learn about subscription options.pp. 368-380
by Ramon Bertran, Alper Buyuktosunoglu, Pradip Bose, Timothy J. Slegel, Gerard Salem, Sean Carey, Richard F. Rizzolo, Thomas Strach
Enabling Realistic Fine-Grain Voltage Scaling with Reconfigurable Power Distribution NetworksFull-text access may be available. Sign in or learn about subscription options.pp. 381-393
by Waclaw Godycki, Christopher Torng, Ivan Bukreyev, Alyssa Apsel, Christopher Batten
Micro-Sliced Virtual Processors to Hide the Effect of Discontinuous CPU Availability for Consolidated SystemsFull-text access may be available. Sign in or learn about subscription options.pp. 394-405
by Jeongseob Ahn, Chang Hyun Park, Jaehyuk Huh
SMiTe: Precise QoS Prediction on Real-System SMT Processors to Improve Utilization in Warehouse Scale ComputersFull-text access may be available. Sign in or learn about subscription options.pp. 406-418
by Yunqi Zhang, Michael A. Laurenzano, Jason Mars, Lingjia Tang
A Front-End Execution Architecture for High Energy EfficiencyFull-text access may be available. Sign in or learn about subscription options.pp. 419-431
by Ryota Shioya, Masahiro Goshima, Hideki Ando
Execution Drafting: Energy Efficiency through Computation DeduplicationFull-text access may be available. Sign in or learn about subscription options.pp. 432-444
by Michael Mckeown, Jonathan Balkind, David Wentzlaff
PPEP: Online Performance, Power, and Energy Prediction Framework and DVFS Space ExplorationFull-text access may be available. Sign in or learn about subscription options.pp. 445-457
by Bo Su, Junli Gu, Li Shen, Wei Huang, Joseph L. Greathouse, Zhiying Wang
NoC Architectures for Silicon Interposer Systems: Why Pay for more Wires when you Can Get them (from your interposer) for Free?Full-text access may be available. Sign in or learn about subscription options.pp. 458-470
by Natalie Enright Jerger, Ajaykumar Kannan, Zimo Li, Gabriel H. Loh
Hi-Rise: A High-Radix Switch for 3D Integration with Single-Cycle ArbitrationFull-text access may be available. Sign in or learn about subscription options.pp. 471-483
by Supreet Jeloka, Reetuparna Das, Ronald G. Dreslinski, Trevor Mudge, David Blaauw
Multi-GPU System Design with Memory NetworksFull-text access may be available. Sign in or learn about subscription options.pp. 484-495
by Gwangsun Kim, Minseok Lee, Jiyun Jeong, John Kim
Dodec: Random-Link, Low-Radix On-Chip NetworksFull-text access may be available. Sign in or learn about subscription options.pp. 496-508
by Haofan Yang, Jyoti Tripathi, Natalie Enright Jerger, Dan Gibson
Wormhole: Wisely Predicting Multidimensional BranchesFull-text access may be available. Sign in or learn about subscription options.pp. 509-520
by Jorge Albericio, Joshua San Miguel, Natalie Enright Jerger, Andreas Moshovos
Bias-Free Branch PredictorFull-text access may be available. Sign in or learn about subscription options.pp. 521-532
by Dibakar Gope, Mikko H. Lipasti
Loop-Aware Memory Prefetching Using Code Block Working SetsFull-text access may be available. Sign in or learn about subscription options.pp. 533-544
by Adi Fuchs, Shie Mannor, Uri Weiser, Yoav Etsion
BuMP: Bulk Memory Access Prediction and StreamingFull-text access may be available. Sign in or learn about subscription options.pp. 545-557
by Stavros Volos, Javier Picorel, Babak Falsafi, Boris Grot
Protean Code: Achieving Near-Free Online Code Transformations for Warehouse Scale ComputersFull-text access may be available. Sign in or learn about subscription options.pp. 558-570
by Michael A. Laurenzano, Yunqi Zhang, Lingjia Tang, Jason Mars
Compiler Support for Optimizing Memory Bank-Level ParallelismFull-text access may be available. Sign in or learn about subscription options.pp. 571-582
by Wei Ding, Diana Guttman, Mahmut Kandemir
Architectural Specialization for Inter-Iteration Loop Dependence PatternsFull-text access may be available. Sign in or learn about subscription options.pp. 583-595
by Shreesha Srinath, Berkin Ilbeyi, Mingxing Tan, Gai Liu, Zhiru Zhang, Christopher Batten
Specializing Compiler Optimizations through Programmable Composition for Dense Matrix ComputationsFull-text access may be available. Sign in or learn about subscription options.pp. 596-608
by Qing Yi, Qian Wang, Huimin Cui
DaDianNao: A Machine-Learning SupercomputerFull-text access may be available. Sign in or learn about subscription options.pp. 609-622
by Yunji Chen, Tao Luo, Shaoli Liu, Shijin Zhang, Liqiang He, Jia Wang, Ling Li, Tianshi Chen, Zhiwei Xu, Ninghui Sun, Olivier Temam
B-Fetch: Branch Prediction Directed Prefetching for Chip-MultiprocessorsFull-text access may be available. Sign in or learn about subscription options.pp. 623-634
by David Kadjo, Jinchun Kim, Prabal Sharma, Reena Panda, Paul Gratz, Daniel Jimenez
PipeCheck: Specifying and Verifying Microarchitectural Enforcement of Memory Consistency ModelsFull-text access may be available. Sign in or learn about subscription options.pp. 635-646
by Daniel Lustig, Michael Pellauer, Margaret Martonosi
Equalizer: Dynamic Tuning of GPU Resources for Efficient ExecutionFull-text access may be available. Sign in or learn about subscription options.pp. 647-658
by Ankit Sethia, Scott Mahlke
COMP: Compiler Optimizations for Manycore ProcessorsFull-text access may be available. Sign in or learn about subscription options.pp. 659-671
by Linhai Song, Min Feng, Nishkam Ravi, Yi Yang, Srimat Chakradhar
Author IndexFreely available from IEEE.pp. 672-674
Publisher's InformationFreely available from IEEE.pp. 676-676
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