Default Cover Image

2016 49th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO)

Oct. 15 2016 to Oct. 19 2016

Taipei, Taiwan

Table of Contents

ProgramFreely available from IEEE.pp. 1-4
MICRO-49 organizing committeeFreely available from IEEE.pp. 1-1
MICRO-49 program committeeFreely available from IEEE.pp. 1-2
MICRO-49 steering committeeFreely available from IEEE.pp. 1-1
External reviewersFreely available from IEEE.pp. 1-6
SponsorsFreely available from IEEE.pp. 1-1
Message from the general chairsFreely available from IEEE.pp. 1-1
Message from the MICRO-49 program co-chairsFreely available from IEEE.pp. 1-2
Dictionary sharing: An efficient cache compression scheme for compressed cachesFull-text access may be available. Sign in or learn about subscription options.pp. 1-12
Perceptron learning for reuse predictionFull-text access may be available. Sign in or learn about subscription options.pp. 1-12
pTask: A smart prefetching scheme for OS intensive applicationsFull-text access may be available. Sign in or learn about subscription options.pp. 1-12
Register sharing for equality predictionFull-text access may be available. Sign in or learn about subscription options.pp. 1-12
Data-centric execution of speculative parallel programsFull-text access may be available. Sign in or learn about subscription options.pp. 1-13
SABRes: Atomic object reads for in-memory rack-scale computingFull-text access may be available. Sign in or learn about subscription options.pp. 1-13
Towards efficient server architecture for virtualized network function deployment: Implications and implementationsFull-text access may be available. Sign in or learn about subscription options.pp. 1-12
Bridging the I/O performance gap for big data workloads: A new NVDIMM-based approachFull-text access may be available. Sign in or learn about subscription options.pp. 1-12
NeSC: Self-virtualizing nested storage controllerFull-text access may be available. Sign in or learn about subscription options.pp. 1-12
MIMD synchronization on SIMT architecturesFull-text access may be available. Sign in or learn about subscription options.pp. 1-14
Efficient kernel synthesis for performance portable programmingFull-text access may be available. Sign in or learn about subscription options.pp. 1-13
GRAPE: Minimizing energy for GPU applications with performance requirementsFull-text access may be available. Sign in or learn about subscription options.pp. 1-13
From high-level deep neural models to FPGAsFull-text access may be available. Sign in or learn about subscription options.pp. 1-12
Stripes: Bit-serial deep neural network computingFull-text access may be available. Sign in or learn about subscription options.pp. 1-12
Cambricon-X: An accelerator for sparse neural networksFull-text access may be available. Sign in or learn about subscription options.pp. 1-12
Fused-layer CNN acceleratorsFull-text access may be available. Sign in or learn about subscription options.pp. 1-12
Lazy release consistency for GPUsFull-text access may be available. Sign in or learn about subscription options.pp. 1-14
Improving energy efficiency of DRAM by exploiting half page row accessFull-text access may be available. Sign in or learn about subscription options.pp. 1-12
OSCAR: Orchestrating STT-RAM cache traffic for heterogeneous CPU-GPU architecturesFull-text access may be available. Sign in or learn about subscription options.pp. 1-13
Contention-based congestion management in large-scale networksFull-text access may be available. Sign in or learn about subscription options.pp. 1-13
Dynamic error mitigation in NoCs using intelligent prediction techniquesFull-text access may be available. Sign in or learn about subscription options.pp. 1-12
Reducing data movement energy via online data clustering and encodingFull-text access may be available. Sign in or learn about subscription options.pp. 1-13
Racer: TSO consistency via race detectionFull-text access may be available. Sign in or learn about subscription options.pp. 1-13
Exploiting semantic commutativity in hardware speculationFull-text access may be available. Sign in or learn about subscription options.pp. 1-12
CANDY: Enabling coherent DRAM caches for multi-node systemsFull-text access may be available. Sign in or learn about subscription options.pp. 1-13
C3D: Mitigating the NUMA bottleneck via coherent DRAM cachesFull-text access may be available. Sign in or learn about subscription options.pp. 1-12
Quantifying and improving the efficiency of hardware-based mobile malware detectorsFull-text access may be available. Sign in or learn about subscription options.pp. 1-13
PoisonIvy: Safe speculation for secure memoryFull-text access may be available. Sign in or learn about subscription options.pp. 1-13
ReplayConfusion: Detecting cache-based covert channel attacks using record and replayFull-text access may be available. Sign in or learn about subscription options.pp. 1-14
Jump over ASLR: Attacking branch predictors to bypass ASLRFull-text access may be available. Sign in or learn about subscription options.pp. 1-13
The Bunker Cache for spatio-value approximationFull-text access may be available. Sign in or learn about subscription options.pp. 1-12
HARE: Hardware accelerator for regular expressionsFull-text access may be available. Sign in or learn about subscription options.pp. 1-12
The microarchitecture of a real-time robot motion planning acceleratorFull-text access may be available. Sign in or learn about subscription options.pp. 1-12
Efficient data supply for hardware accelerators with prefetching and access/execute decouplingFull-text access may be available. Sign in or learn about subscription options.pp. 1-12
An ultra low-power hardware accelerator for automatic speech recognitionFull-text access may be available. Sign in or learn about subscription options.pp. 1-12
Co-designing accelerators and SoC interfaces using gem5-AladdinFull-text access may be available. Sign in or learn about subscription options.pp. 1-12
Chainsaw: Von-neumann accelerators to leverage fused instruction chainsFull-text access may be available. Sign in or learn about subscription options.pp. 1-14
A patch memory system for image processing and computer visionFull-text access may be available. Sign in or learn about subscription options.pp. 1-13
Redefining QoS and customizing the power management policy to satisfy individual mobile usersFull-text access may be available. Sign in or learn about subscription options.pp. 1-12
Ti-states: Processor power management in the temperature inversion regionFull-text access may be available. Sign in or learn about subscription options.pp. 1-13
Improving bank-level parallelism for irregular applicationsFull-text access may be available. Sign in or learn about subscription options.pp. 1-12
Delegated persist orderingFull-text access may be available. Sign in or learn about subscription options.pp. 1-13
Spectral profiling: Observer-effect-free profiling by monitoring EM emanationsFull-text access may be available. Sign in or learn about subscription options.pp. 1-11
Path confidence based lookahead prefetchingFull-text access may be available. Sign in or learn about subscription options.pp. 1-12
Continuous runahead: Transparent hardware acceleration for memory intensive workloadsFull-text access may be available. Sign in or learn about subscription options.pp. 1-12
Author indexFreely available from IEEE.pp. 1-29
Showing 71 out of 71