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Memory Technology, Design and Testin, IEEE International Workshop on

Aug. 9 2004 to Aug. 10 2004

San Jose, California, USA

ISSN: 1087-4852

ISBN: 0-7695-2193-2

Table of Contents

Records of the 2004 International Workshop on Memory Technology, Design and TestingFreely available from IEEE.pp. iii-iii
Fast error-correcting circuits for fault-tolerant memoryFull-text access may be available. Sign in or learn about subscription options.pp. 8-12
by E. Ou, W. Yang
Tag skipping technique using WTS buffer for optimal low power cache designFull-text access may be available. Sign in or learn about subscription options.pp. 13-18
by A. Akaaboune, N. Botros, J. Alghazo
SF-LRU cache replacement algorithmFull-text access may be available. Sign in or learn about subscription options.pp. 19-24
by J. Alghazo, A. Akaaboune, N. Botros
The effectiveness of the scan test and its new variantsFull-text access may be available. Sign in or learn about subscription options.pp. 26-31
by A.J. van de Goor, S. Hamdioui, Z. Al-Ars
Influence of bit line twisting on the faulty behavior of DRAMsFull-text access may be available. Sign in or learn about subscription options.pp. 32-37
by Z. Al-Ars, M. Herzog, I. Schanstra, A.J. van de Goor
Markov models of fault-tolerant memory systems under SEUFull-text access may be available. Sign in or learn about subscription options.pp. 38-43
by L. Schiano, M. Ottavi, F. Lombardi
Tutorial on magnetic tunnel junction magnetoresistive random-access memoryFull-text access may be available. Sign in or learn about subscription options.pp. 46-51
by B.F. Cockburn
The state-of-art and future trends in testing embedded memoriesFull-text access may be available. Sign in or learn about subscription options.pp. 54-59
by S. Hamdioui, G. Gaydadjiev, A.J. van de Goor
Built-in self-test and repair (BISTR) techniques for embedded RAMsFull-text access may be available. Sign in or learn about subscription options.pp. 60-64
by Shyue-Kung Lu, Shih-Chang Huang
A parallel built-in diagnostic scheme for multiple embedded memoriesFull-text access may be available. Sign in or learn about subscription options.pp. 65-69
by Li-Ming Denq, Rei-Fu Huang, Cheng-Wen Wu, Yeong-Jar Chang, Wen-Ching Wu
Micro programmable built-in self repair for SRAMsFull-text access may be available. Sign in or learn about subscription options.pp. 72-77
by R. Zappa, C. Selva, D. Rimondi, C. Torelli, M. Crestan, G. Mastrodomenico, L. Albani
A novel method for silicon configurable test flow and algorithms for testing, debugging and characterizing different types of embedded memories through a shared controllerFull-text access may be available. Sign in or learn about subscription options.pp. 78-83
by S. Bahl, B. Singh
A programmable built-in self-diagnosis for embedded SRAMFull-text access may be available. Sign in or learn about subscription options.pp. 84-89
by C. Selva, C. Torelli, D. Rimondi, R. Zappa, S. Corbani, G. Mastrodomenico, L. Albani
An integrated memory self test and EDA solutionFull-text access may be available. Sign in or learn about subscription options.pp. 92-95
by R. Dean Adams, R. Abbott, Xiaoling Bai, D. Burek, E. MacDonald
A BIST algorithm for bit/group write enable faults in SRAMsFull-text access may be available. Sign in or learn about subscription options.pp. 98-101
by S. Adham, B. Nadeau-Dostie
Session 2: Fast ECC and Efficient Cache Controllers
Fast Error-Correcting Circuits for Fault-Tolerant MemoryFull-text access may be available. Sign in or learn about subscription options.pp. 8-12
by Elaine Ou, Woodward Yang
Embedded memory reliability: the SER challengeFull-text access may be available. Sign in or learn about subscription options.pp. 104-110
by N. Derhacobian, V.A. Vardanian, Y. Zorian
Session 2: Fast ECC and Efficient Cache Controllers
Tag Skipping Technique Using WTS Buffer for Optimal Low Power Cache DesignFull-text access may be available. Sign in or learn about subscription options.pp. 13-18
by Adil Akaaboune, Nazeih Botros, Jaafar Alghazo
Do we need anything more than single bit error correction (ECC)?Full-text access may be available. Sign in or learn about subscription options.pp. 111-116
by M. Spica, T.M. Mak
Session 2: Fast ECC and Efficient Cache Controllers
SF-LRU Cache Replacement AlgorithmFull-text access may be available. Sign in or learn about subscription options.pp. 19-24
by Jaafar Alghazo, Adil Akaaboune, Nazeih Botros
Redundancy - it's not just for defects any moreFull-text access may be available. Sign in or learn about subscription options.pp. 117-120
by R. Aitken
Session 3: Memory Fault Coverage and Test Analysis
The Effectiveness of the Scan Test and Its New VariantsFull-text access may be available. Sign in or learn about subscription options.pp. 26-31
by Ad J. van de Goor, Said Hamdioui, Zaid Al-Ars
Session 3: Memory Fault Coverage and Test Analysis
Influence of Bit Line Twisting on the Faulty Behavior of DRAMsFull-text access may be available. Sign in or learn about subscription options.pp. 32-37
by Zaid Al-Ars, Martin Herzog, Ivo Schanstra, Ad J. van de Goor
Session 3: Memory Fault Coverage and Test Analysis
Markov Models of Fault-Tolerant Memory Systems under SEUFull-text access may be available. Sign in or learn about subscription options.pp. 38-43
by Luca Schiano, Marco Ottavi, Fabrizio Lombardi
Session 5: Embedded Memory Test Trends and Future
The State-of-Art and Future Trends in Testing Embedded MemoriesFull-text access may be available. Sign in or learn about subscription options.pp. 54-59
by Said Hamdioui, Georgi Gaydadjiev, Ad J. van de Goor
Session 5: Embedded Memory Test Trends and Future
Built-in Self-Test and Repair (BISTR) Techniques for Embedded RAMsFull-text access may be available. Sign in or learn about subscription options.pp. 60-64
by Shyue-Kung Lu, Shih-Chang Huang
Session 5: Embedded Memory Test Trends and Future
A Parallel Built-in Diagnostic Scheme for Multiple Embedded MemoriesFull-text access may be available. Sign in or learn about subscription options.pp. 65-69
by Li-Ming Denq, Rei-Fu Huang, Cheng-Wen Wu, Yeong-Jar Chang, Wen-Ching Wu
Session 6: Industrial Practices on BIST, BISD and BISR
Micro Programmable Built-In Self Repair for SRAMsFull-text access may be available. Sign in or learn about subscription options.pp. 72-77
by R. Zappa, C. Selva, D. Rimondi, C. Torelli, M. Crestan, G. Mastrodomenico, L. Albani
Session 6: Industrial Practices on BIST, BISD and BISR
A Novel Method for Silicon Configurable Test Flow and Algorithms for Testing, Debugging and Characterizing Different Types of Embedded Memories through a Shared ControllerFull-text access may be available. Sign in or learn about subscription options.pp. 78-83
by Swapnil Bahl, Balwant Singh
Session 6: Industrial Practices on BIST, BISD and BISR
A Programmable Built-in Self-Diagnosis for Embedded SRAMFull-text access may be available. Sign in or learn about subscription options.pp. 84-89
by Carolina Selva, Cosimo Torelli, Danilo Rimondi, Rita Zappa, Stefano Corbani, Giovanni Mastrodomenico, Lara Albani
Session 7: EDA Solutions to Test and Repair Memories
An Integrated Memory Self Test and EDA SolutionFull-text access may be available. Sign in or learn about subscription options.pp. 92-95
by R. Dean Adams, Robert Abbott, Xiaoliang Bai, Dwayne Burek, Eric MacDonald
Session 7: EDA Solutions to Test and Repair Memories
A BIST Algorithm for Bit/Group Write Enable Faults in SRAMsFull-text access may be available. Sign in or learn about subscription options.pp. 98-101
by Saman Adham, Benoit Nadeau-Dostie
Session 8: Making Memories More Reliable
Embedded Memory Reliability: The SER ChallengeFull-text access may be available. Sign in or learn about subscription options.pp. 104-110
by N. Derhacobian, V. A. Vardanian, Y. Zorian
Session 8: Making Memories More Reliable
Do We Need Anything More Than Single Bit Error Correction (ECC)?Full-text access may be available. Sign in or learn about subscription options.pp. 111-116
by Michael Spica, TM Mak
Session 8: Making Memories More Reliable
Redundancy & It?s Not Just for Defects AnymoreFull-text access may be available. Sign in or learn about subscription options.pp. 117-120
by Rob Aitken
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