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2010 IEEE/ACM International Symposium on Nanoscale Architectures

June 17 2010 to June 18 2010

Anaheim, CA

Table of Contents

[Front matter]Freely available from IEEE.pp. i-ix
Papers
Compact method for modeling and simulation of memristor devices: Ion conductor chalcogenide-based memristor devicesFull-text access may be available. Sign in or learn about subscription options.pp. 1-4
by Robinson E. Pino, James W. Bohl, Nathan McDonald, Bryant Wysocki, Peter Rozwood, Kristy A. Campbell, Antonio Oblea, Achyut Timilsina
Papers
Memristor based programmable threshold logic arrayFull-text access may be available. Sign in or learn about subscription options.pp. 5-10
by Jeyavijayan Rajendran, Harika Manem, Ramesh Karri, Garrett S. Rose
Papers
Towards logic functions as the deviceFull-text access may be available. Sign in or learn about subscription options.pp. 11-16
by Prasad Shabadi, Alexander Khitun, Pritish Narayanan, Mingqiang Bao, Israel Koren, Kang L. Wang, C. Andras Moritz
Papers
High throughput and low power dissipation in QCA pipelines using Bennett clockingFull-text access may be available. Sign in or learn about subscription options.pp. 17-22
by Marco Ottavi, Salvatore Pontarelli, Erik DeBenedictis, Adelio Salsano, Peter Kogge, Fabrizio Lombardi
Papers
Fast equivalence-checking for quantum circuitsFull-text access may be available. Sign in or learn about subscription options.pp. 23-28
by Shigeru Yamashita, Igor L. Markov
Papers
Design and comparison of NML systolic architecturesFull-text access may be available. Sign in or learn about subscription options.pp. 29-34
by Michael Crocker, X. Sharon Hu, Michael Niemier
Papers
UNION: A unified inter/intra-chip optical network for chip multiprocessorsFull-text access may be available. Sign in or learn about subscription options.pp. 35-40
by Xiaowen Wu, Yaoyao Ye, Wei Zhang, Weichen Liu, Mahdi Nikdast, Xuan Wang, Jiang Xu
Papers
Fault modeling for FinFET circuitsFull-text access may be available. Sign in or learn about subscription options.pp. 41-46
by Muzaffer O. Simsir, Ajay Bhoj, Niraj K. Jha
Papers
Reducing transistor count in clocked standard cells with ambipolar double-gate FETsFull-text access may be available. Sign in or learn about subscription options.pp. 47-52
by K. Jabeur, D. Navarro, I. O'Connor, P. E. Gaillardon, M. H. Ben Jamaa, F. Clermidy
Papers
NanoV: Nanowire-based VLSI designFull-text access may be available. Sign in or learn about subscription options.pp. 53-58
by Muzaffer O. Simsir, Niraj K. Jha
Papers
Stochastic nanoscale addressing for logicFull-text access may be available. Sign in or learn about subscription options.pp. 59-64
by Eric Rachlin, John E. Savage
Papers
Regular fabric design with ambipolar CNTFETs for FPGA and structured ASIC applicationsFull-text access may be available. Sign in or learn about subscription options.pp. 65-70
by Michele De Marchi, M. Haykel Ben Jamaa, Giovanni De Micheli
Papers
Design methodology for Carbon Nanotube based circuits in the presence of metallic tubesFull-text access may be available. Sign in or learn about subscription options.pp. 71-76
by Rehman Ashraf, Rajeev K. Nain, Malgorzata Chrzanowska-Jeske, Siva G. Narendra
Papers
Intel LVS logic as a combinational logic paradigm in CNT technologyFull-text access may be available. Sign in or learn about subscription options.pp. 77-81
by Bao Liu, Zhen Cao, Jun Tao, Xuan Zeng, Pushan Tang, Philip H.-S. Wong
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