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2012 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH 2012)

July 4 2012 to July 6 2012

Amsterdam

Table of Contents

[Front matter]Freely available from IEEE.pp. i-xi
Ambipolar circuits for analog, mixed-signal, and radio-frequency applicationsFull-text access may be available. Sign in or learn about subscription options.pp. 1-6
by Kartik Mohanram, Xuebei Yang, Guanxiong Liu, Masoud Rostami, Alexander Balandin
Ambipolar double gate CNTFETs based reconfigurable Logic cellsFull-text access may be available. Sign in or learn about subscription options.pp. 7-13
by Kotb Jabeur, Ian O'Connor, David Navarro, Sébastien Beux
Low-power design technique with ambipolar double gate devicesFull-text access may be available. Sign in or learn about subscription options.pp. 14-21
by Kotb Jabeur, Ian O'Connor, David Navarro, Sébastien Le Beux
Gate-level modeling for CMOS circuit simulation with ultimate FinFETsFull-text access may be available. Sign in or learn about subscription options.pp. 22-29
by Nicolas Chevillon, Morgan Madec, Christophe Lallement
Design exploration of ultra-low power non-volatile memory based on topological insulatorFull-text access may be available. Sign in or learn about subscription options.pp. 30-35
by Yuhao Wang, Hao Yu
A conventional design for CLB implementation of a FPGA in Quantum-dot Cellular Automata (QCA)Full-text access may be available. Sign in or learn about subscription options.pp. 36-42
by Moein Kianpour, Reza Sabbaghi-Nadooshan
Introducing OVP awareness to achieve an efficient permanent defect locatingFull-text access may be available. Sign in or learn about subscription options.pp. 43-49
by Tanvir Ahmed, Jun Yao, Yasuhiko Nakashima
Irreversibility induced density limits and logical reversiblity in nanocircuitsFull-text access may be available. Sign in or learn about subscription options.pp. 50-54
by Ismo Hänninen, Jarmo Takala
Process/design co-optimization of regular logic tiles for double-gate silicon nanowire transistorsFull-text access may be available. Sign in or learn about subscription options.pp. 55-60
by Shashikanth Bobba, Pierre-Emmanuel Gaillardon, Jian Zhang, Michele De Marchi, Davide Sacchetto, Yusuf Leblebici, Giovanni De Micheli
Ambipolar independent double gate FET logicFull-text access may be available. Sign in or learn about subscription options.pp. 61-68
by Ian O'Connor, Kotb Jabeur, Sébastien Le Beux, David Navarro
Ternary volatile random access memory based on heterogeneous graphene-CMOS fabricFull-text access may be available. Sign in or learn about subscription options.pp. 69-76
by Santosh Khasanvis, K. M. Masum Habib, Mostafizur Rahman, Pritish Narayanan, Roger K. Lake, Csaba Andras Moritz
Macromodeling a phase change memory (PCM) cell by HSPICEFull-text access may be available. Sign in or learn about subscription options.pp. 77-84
by Pilin Junsangsri, Fabrizio Lombardi, Jie Han
Crossbar architecture based on 2R complementary resistive switching memory cellFull-text access may be available. Sign in or learn about subscription options.pp. 85-92
by W.S. Zhao, Y. Zhang, J.O Klein, D. Querlioz, D. Chabi, D. Ravelosona, C. Chappert, J.M. Portal, M. Bocquet, H. Aziza, D. Deleruyelle, C. Muller
A Monte Carlo analysis of a write method used in passive nanoelectronic crossbarsFull-text access may be available. Sign in or learn about subscription options.pp. 93-100
by Arne Heittmann, Tobias G. Noll
RRAM-based FPGA for “normally off, instantly on” applicationsFull-text access may be available. Sign in or learn about subscription options.pp. 101-108
by O. Turkyilmaz, S. Onkaraiah, M. Reyboz, F. Clermidy, Costin Anghel Hraziia, J. Portal, Marc Bocquet
Statistical reliability analysis of NBTI impact on FinFET SRAMs and mitigation technique using independent-gate devicesFull-text access may be available. Sign in or learn about subscription options.pp. 109-115
by Yao Wang, Sorin D. Cotofana, Liang Fang
A Markovian, variation-aware circuit-level aging modelFull-text access may be available. Sign in or learn about subscription options.pp. 116-122
by Nicoleta Cucu Laurenciu, Sorin Dan Cotofana
Zero-performance-overhead online fault detection and diagnosis in 3D stacked integrated circuitsFull-text access may be available. Sign in or learn about subscription options.pp. 123-130
by Saleh Safiruddin, Mihai Lefter, Demid Borodin, George Voicu, Sorin Dan Cotofana
Design and reliability analysis of multiple valued logic gates using carbon nanotube FETsFull-text access may be available. Sign in or learn about subscription options.pp. 131-138
by Jinghang Liang, Linbin Chen, Jie Han, Fabrizio Lombardi
Emitter-coupled spin-transistor logicFull-text access may be available. Sign in or learn about subscription options.pp. 139-145
by Joseph S. Friedman, Yehea I. Ismail, Gokhan Memik, Alan V. Sahakian, Bruce W. Wessels
Room temperature double gate Single Electron Transistor based standard cell libraryFull-text access may be available. Sign in or learn about subscription options.pp. 146-151
by Mohamed Amine Bounouar, Arnaud Beaumont, Khalil El Hajjam, Francis Calmon, Dominique Drouin
Cell design and comparative evaluation of a novel 1T memristor-based memoryFull-text access may be available. Sign in or learn about subscription options.pp. 152-159
by Vikas Sakode, Fabrizio Lombardi, Jie Han
ToPoliNano: Nanoarchitectures design made realFull-text access may be available. Sign in or learn about subscription options.pp. 160-167
by S. Frache, D. Chiabrando, M. Graziano, F. Riente, G. Turvani, M. Zamboni
A novel write-scheme for data integrity in memristor-based crossbar memoriesFull-text access may be available. Sign in or learn about subscription options.pp. 168-173
by Angelo Giuseppe Ruotolo, Marco Ottavi, Salvatore Pontarelli, Fabrizio Lombardi
Stigmergic search with Single Electron Tunneling technology based Memory Enhanced HubsFull-text access may be available. Sign in or learn about subscription options.pp. 174-180
by Saleh Safiruddin, Sorin Cotofana, Ferdinand Peper
Synthesis of topological quantum circuitsFull-text access may be available. Sign in or learn about subscription options.pp. 181-187
by Alexandru Paler, Simon Devitt, Kae Nemoto, Ilia Polian
Spintronic Threshold Logic Array (STLA) - a compact, low leakage, non-volatile gate array architectureFull-text access may be available. Sign in or learn about subscription options.pp. 188-195
by Nishant S. Nukala, Niranjan Kulkarni, Sarma Vrudhula
Spin wave nanofabric updateFull-text access may be available. Sign in or learn about subscription options.pp. 196-202
by J. G. Alzate, P. Upadhyaya, M. Lewis, J. Nath, Y. T. Lin, K. Wong, S. Cherepov, P. Khalili Amiri, K.L. Wang, J. Hockel, A. Bur, G. P. Carman, S. Bender, Y. Tserkovnyak, J. Zhu, Y-J Chen, I. N. Krivorotov, J. Katine, J. Langer, P. Shabadi, S. Khasanvis, S. Narayanan, C. A. Moritz, A. Khitun
Bioinspired networks with nanoscale memristive devices that combine the unsupervised and supervised learning approachesFull-text access may be available. Sign in or learn about subscription options.pp. 203-210
by D. Querlioz, W. S. Zhao, P. Dollfus, J.-O. Klein, O. Bichler, C. Gamrat
Ultra low energy analog image processing using spin based neuronsFull-text access may be available. Sign in or learn about subscription options.pp. 211-217
by Mrigank Sharad, Charles Augustine, Georgios Panagopoulos, Kaushik Roy
RRAM-based adaptive neural logic block for implementing non-linearly separable functions in a single layerFull-text access may be available. Sign in or learn about subscription options.pp. 218-225
by Michael Soltiz, Cory Merkel, Dhireesha Kudithipudi, Garrett S. Rose
Memristor-based reservoir computingFull-text access may be available. Sign in or learn about subscription options.pp. 226-232
by Manjari S. Kulkarni, Christof Teuscher
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