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2009 2nd International Workshop on Network on Chip Architectures (NoCArc 2009)

Dec. 12 2009 to Dec. 12 2009

New York, NY

Table of Contents

Message from the ChairsFull-text access may be available. Sign in or learn about subscription options.pp. iii-iv
by Maurizio Palesi, Shashi Kumar
Technical program committeeFreely available from IEEE.pp. v-vi
Toward a science for future NoC designFull-text access may be available. Sign in or learn about subscription options.pp. 1-2
by R. Marculescu
Router microarchitecture and scalability of ring topology in on-chip networksFull-text access may be available. Sign in or learn about subscription options.pp. 5-10
by J. Kim, Hanjoon Kim
Breaking adaptive multicast deadlock by virtual channel address/data FIFO decouplingFull-text access may be available. Sign in or learn about subscription options.pp. 11-16
by Ka-Ming Keung, A. Tyagi
Adaptive router architecture based on traffic behavior observabilityFull-text access may be available. Sign in or learn about subscription options.pp. 17-22
by D. Matos, C. Concatto, A. Kologeski, L. Carro, F. Kastensmidt, A. Susin, M. Kreutz
Path-based, Randomized, Oblivious, Minimal routingFull-text access may be available. Sign in or learn about subscription options.
by Myong Hyon Cho, Mieszko Lis, Keun Sup Shim, Michel Kinsy, Srinivas Devadas
Architecture design principles for the integration of synchronization interfaces into network-on-chip switchesFull-text access may be available. Sign in or learn about subscription options.pp. 31-36
by D. Ludovici, A. Strano, D. Bertozzi
Yield enhancement by robust application-specific mapping on network-on-chipsFull-text access may be available. Sign in or learn about subscription options.pp. 37-42
by A. Dutta Choudhury, G. Palermo, C. Silvano, V. Zaccaria
The era of many-modules SoC: revisiting the NoC mapping problemFull-text access may be available. Sign in or learn about subscription options.pp. 43-48
by I. Walter, I. Cidon, A. Kolodny, D. Sigalov
A performance evaluation of 2D-mesh, ring, and crossbar interconnects for chip multi-processorsFull-text access may be available. Sign in or learn about subscription options.pp. 51-56
by J.C. Villanueva, J. Flich, J. Duato, H. Eberle, N. Gura, W. Olesinski
Segment gating for static energy reduction in networks-on-chipFull-text access may be available. Sign in or learn about subscription options.pp. 57-62
by K.C. Hale, B. Grot, S.W. Keckler
System-level exploration of run-time clusterization for energy-efficient on-chip communicationFull-text access may be available. Sign in or learn about subscription options.pp. 63-68
by Liang Guang, E. Nigussie, H. Tenhunen
Hybrid wireless network on chip: A new paradigm in multi-core designFull-text access may be available. Sign in or learn about subscription options.pp. 71-76
by P.P. Pande, A. Ganguly, K. Chang, C. Teuscher
Scalable arbitration of partitioned bus interconnection networks in 3D-IC systemsFull-text access may be available. Sign in or learn about subscription options.pp. 77-82
by K. Ireland, J. Jezak, S. Levitan, D. Chiarulli
Wire cost and communication analysis of self-assembled interconnect models for networks-on-chipFull-text access may be available. Sign in or learn about subscription options.pp. 83-88
by C. Teuscher, N. Parashar, M. Mote, N. Hergert, J. Aherne
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