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2018 11th International Workshop on Network on Chip Architectures (NoCArc)

Oct. 20 2018 to Oct. 20 2018

Fukuoka, Japan

Table of Contents

[Copyright notice]Freely available from IEEE.pp. i-i
Table of contentsFreely available from IEEE.pp. i-ii
NoCArc 2018 Message from the ChairsFreely available from IEEE.pp. i-i
NoCArc 2018 CommitteesFreely available from IEEE.pp. i-i
NoCArc 2018 Technical Program CommitteeFreely available from IEEE.pp. i-i
NoCArc 2018 Steering CommitteeFreely available from IEEE.pp. i-i
Value-Based Deep Learning Hardware AccelerationFull-text access may be available. Sign in or learn about subscription options.pp. 1-1
Hierarchical and Dependency-Aware Task Mapping for NoC-based SystemsFull-text access may be available. Sign in or learn about subscription options.pp. 1-6
NN-Noxim: High-Level Cycle-Accurate NoC-based Neural Networks SimulatorFull-text access may be available. Sign in or learn about subscription options.pp. 1-5
Keynote Talk: 3D Core-based SoC Testing for Low Power and TSV Count MinimizationFull-text access may be available. Sign in or learn about subscription options.pp. 1-1
Efficient Router Bypass via Hybrid Flow ControlFull-text access may be available. Sign in or learn about subscription options.pp. 1-6
3D MAX: A Maximally Adaptive Routing Method for VC-less 3D Mesh-based Networks-on-ChipFull-text access may be available. Sign in or learn about subscription options.pp. 1-6
NoCArc 2018 IndexFreely available from IEEE.pp. i-i
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