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Proceedings 2000 International Conference on Parallel Architectures and Compilation Techniques (Cat. No.PR00622)

Oct. 15 2000 to Oct. 19 2000

Philadelphia, Pennsylvania

ISSN: 1089-795X

ISBN: 0-7695-0622-4

Table of Contents

Proceedings 2000 International Conference on Parallel Architectures and Compilation Techniques (Cat. No.PR00622)Freely available from IEEE.pp. iii-iii
IntroductionFreely available from IEEE.pp. viii
Organizing CommitteeFreely available from IEEE.pp. ix
Program CommitteeFreely available from IEEE.pp. x
ReviewersFreely available from IEEE.pp. xi
Keynote
?New Challenges in Microarchitecture and Compiler Design?Full-text access may be available. Sign in or learn about subscription options.
by Fred Pollack, Intel Corporation
Register Allocation and Analysis
Register Queues: A New Hardware/Software Approach to Efficient Software PipeliningFull-text access may be available. Sign in or learn about subscription options.pp. 3
by Mikhail Smelyanskiy, Gary S. Tyson, Edward S. Davidson
Register Allocation and Analysis
Global Register PartitioningFull-text access may be available. Sign in or learn about subscription options.pp. 13
by Jason Hiser, Steve Carr, Philip Sweany
Register Allocation and Analysis
Region Formation Analysis with Demand-Driven Inlining for Region-Based OptimizationFull-text access may be available. Sign in or learn about subscription options.pp. 24
by Tom Way, Ben Breech, Lori Pollock
Architectural Design
aSOC: A Scalable, Single-Chip Communications ArchitectureFull-text access may be available. Sign in or learn about subscription options.pp. 37
by Jian Liang, Sriram Swaminathan, Russell Tessier
Architectural Design
Address Partitioning in DSM Clusters with Parallel Coherence ControllersFull-text access may be available. Sign in or learn about subscription options.pp. 47
by Babak Falsafi, Ilanthiraiyan Pragaspathy
Architectural Design
Custom Wide Counterflow Pipelines for High-Performance Embedded ApplicationsFull-text access may be available. Sign in or learn about subscription options.pp. 57
by Bruce R. Childers, Jack W. Davidson
Optimizations and Opportunities
A Lightweight Algorithm for Dynamic If-Conversion during Dynamic OptimizationFull-text access may be available. Sign in or learn about subscription options.pp. 71
by Kim M. Hazelwood, Thomas M. Conte
Optimizations and Opportunities
Exploring the Limits of Sub-Word Level ParallelismFull-text access may be available. Sign in or learn about subscription options.pp. 81
by Kevin Scott, Jack Davidson
Optimizations and Opportunities
The Dynamic Trace Memorization Reuse TechniqueFull-text access may be available. Sign in or learn about subscription options.pp. 92
by Amarildo T. da Costa, Felipe M. G. França, Eliseu M.C. Filho
Optimizations and Opportunities
Exploring Sub-Block Value Reuse for Superscalar ProcessorsFull-text access may be available. Sign in or learn about subscription options.pp. 100
by Jian Huang, David J. Lilja
Keynote
?Dynamic Optimization: An Online Opportunity?Full-text access may be available. Sign in or learn about subscription options.
by Michael Smith
High Performance Memory Techniques
Hiding Relaxed Memory Consistency with CompilersFull-text access may be available. Sign in or learn about subscription options.pp. 111
by Jaejin Lee, David A. Padua
High Performance Memory Techniques
Neighborhood Prefetching on Multiprocessors Using Instruction HistoryFull-text access may be available. Sign in or learn about subscription options.pp. 123
by David M. Koppelman
High Performance Memory Techniques
Characterization of Silent StoresFull-text access may be available. Sign in or learn about subscription options.pp. 133
by Gordon B. Bell, Kevin M. Lepak, Mikko H. Lipasti
Speculation and Prediction
On Some Implementation Issues for Value Prediction on Wide-Issue ILP ProcessorsFull-text access may be available. Sign in or learn about subscription options.pp. 145
by Sang-Jeong Lee, Pen-Chung Yew
Speculation and Prediction
A Unified Compiler Framework for Control and Data SpeculationFull-text access may be available. Sign in or learn about subscription options.pp. 157
by Roy Dz-ching Ju, Kevin Nomura, Uma Mahadevan, Le-Chun Wu
Speculation and Prediction
Applying Data Speculation in Modulo Scheduled LoopsFull-text access may be available. Sign in or learn about subscription options.pp. 169
by Uma Mahadevan, Kevin Nomura, Roy Dz-ching Ju, Rick Hank
Branch Prediction
Branch Prediction in Multi-Threaded ProcessorsFull-text access may be available. Sign in or learn about subscription options.pp. 179
by Jayanth Gummaraju, Manoj Franklin
Branch Prediction
The Effect of Code Reordering on Branch PredictionFull-text access may be available. Sign in or learn about subscription options.pp. 189
by Alex Ramirez, Josep L. Larriba-Pey, Mateo Valero
Branch Prediction
A Taxonomy of Branch Mispredictions, and Alloyed Prediction as a Robust Solution to Wrong-History MispredictionsFull-text access may be available. Sign in or learn about subscription options.pp. 199
by Kevin Skadron, Margaret Martonosi, Douglas W. Clark
Branch Prediction
Dynamic Branch Prediction for a VLIW ProcessorFull-text access may be available. Sign in or learn about subscription options.pp. 207
by Jan Hoogerbrugge
Keynote
?Blue Gene?Full-text access may be available. Sign in or learn about subscription options.
by Monty Denneau, IBM T.J. Watson Research Center
Parallel Computation
Fine Grained Multithreading with Process CalculiFull-text access may be available. Sign in or learn about subscription options.pp. 217
by Luís Lopes, Fernando Silva, Vasco T. Vasconcelos
Parallel Computation
Data Relation Vectors: A New Abstraction for Data OptimizationsFull-text access may be available. Sign in or learn about subscription options.pp. 227
by Mahmut Kandemir, J. Ramanujam
Parallel Computation
Combined Selection of Tile Sizes and Unroll Factors Using Iterative CompilationFull-text access may be available. Sign in or learn about subscription options.pp. 237
by T. Kisuki, P.M.W. Knijnenburg, M.F.P. O'Boyle
Applications
Faster FFTs via Architecture-CognizanceFull-text access may be available. Sign in or learn about subscription options.pp. 249
by Kang Su Gatlin, Larry Carter
Applications
Hybrid Parallel Circuit Simulation ApproachesFull-text access may be available. Sign in or learn about subscription options.pp. 261
by Edwin Naroska, Uwe Schwiegelshohn, Rung-Ji Shang, Feipei Lai
Applications
Multithreaded Programming of PC ClustersFull-text access may be available. Sign in or learn about subscription options.pp. 271
by Martin Schulz
Instruction Scheduling
A Fast Algorithm for Scheduling Instructions with Deadline Constraints on RISC ProcessorsFull-text access may be available. Sign in or learn about subscription options.pp. 281
by Hui Wu, Joxan Jaffar, Roland Yap
Instruction Scheduling
Instruction Scheduling for Clustered VLIW DSPsFull-text access may be available. Sign in or learn about subscription options.pp. 291
by Rainer Leupers
Instruction Scheduling
Efficient Backtracking Instruction SchedulersFull-text access may be available. Sign in or learn about subscription options.pp. 301
by Santosh G. Abraham, Waleed M. Meleis, Ivan D. Baev
Instruction Scheduling
Author IndexFreely available from IEEE.pp. 309
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