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16th International Conference on Parallel Architecture and Compilation Techniques (PACT 2007)

Sept. 15 2007 to Sept. 19 2007

Brasov

Table of Contents

16th International Conference on Parallel Architecture and Compilation Techniques-TitleFreely available from IEEE.
16th International Conference on Parallel Architecture and Compilation Techniques-CopyrightFreely available from IEEE.
16th International Conference on Parallel Architecture and Compilation Techniques - TOCFreely available from IEEE.
Introduction
Message from the General ChairFreely available from IEEE.pp. x
Introduction
Message from the Program ChairFreely available from IEEE.pp. xi
Introduction
Organizing CommitteeFreely available from IEEE.pp. xii
Introduction
Program CommitteeFreely available from IEEE.pp. xiii
Introduction
KeynotesFull-text access may be available. Sign in or learn about subscription options.pp. xiv-xvii
Introduction
SponsorsFreely available from IEEE.pp. xviii
Hardware Track (Session 1): Systems
Architectural Support for the Stream Execution Model on General-Purpose ProcessorsFull-text access may be available. Sign in or learn about subscription options.pp. 3-12
by Jayanth Gummaraju, Mattan Erez, Joel Coburn, Mendel Rosenblum, William J. Dally
Hardware Track (Session 1): Systems
A Flexible Heterogeneous Multi-Core ArchitectureFull-text access may be available. Sign in or learn about subscription options.pp. 13-24
by Miquel Pericas, Adrian Cristal, Francisco J. Cazorla, Ruben Gonzalez, Daniel A. Jimenez, Mateo Valero
Hardware Track (Session 1): Systems
Improving Performance Isolation on Chip Multiprocessors via an Operating System SchedulerFull-text access may be available. Sign in or learn about subscription options.pp. 25-38
by Alexandra Fedorova, Margo Seltzer, Michael D. Smith
An Energy Efficient Parallel Architecture Using Near Threshold OperationFull-text access may be available. Sign in or learn about subscription options.pp. 175-188
by Ronald G. Dreslinski, Bo Zhai, Trevor Mudge, David Blaauw, Dennis Sylvester
Software Track (Session 2): Pipelining
Software-Pipelining on Multi-Core ArchitecturesFull-text access may be available. Sign in or learn about subscription options.pp. 39-48
by Alban Douillet, Guang R. Gao
Software Track (Session 2): Pipelining
Speculative Decoupled Software PipeliningFull-text access may be available. Sign in or learn about subscription options.pp. 49-59
by Neil Vachharajani, Ram Rangan, Easwaran Raman, Matthew J. Bridges, Guilherme Ottoni, David I. August
Software Track (Session 2): Pipelining
Rotating Register Allocation for Enhanced Pipeline SchedulingFull-text access may be available. Sign in or learn about subscription options.pp. 60-72
by Suhyun Kim, Soo-Mook Moon
Hardware Track (Session 3): Verification & Security
Unified Architectural Support for Soft-Error Protection or Software Bug DetectionFull-text access may be available. Sign in or learn about subscription options.pp. 73-82
by Martin Dimitrov, Huiyang Zhou
Hardware Track (Session 3): Verification & Security
Verification-Aware Microprocessor DesignFull-text access may be available. Sign in or learn about subscription options.pp. 83-93
by Anita Lungu, Daniel J. Sorin
Hardware Track (Session 3): Verification & Security
I2SEMS: Interconnects-Independent Security Enhanced Shared Memory Multiprocessor SystemsFull-text access may be available. Sign in or learn about subscription options.pp. 94-103
by Manhee Lee, Minseon Ahn, Eun Jung Kim
Hardware Track (Session 3): Verification & Security
Error Detection Using Dynamic Dataflow VerificationFull-text access may be available. Sign in or learn about subscription options.pp. 104-118
by Albert Meixner, Daniel J. Sorin
Software Track (Session 4): Optimizations
Extending Object-Oriented Optimizations for Concurrent ProgramsFull-text access may be available. Sign in or learn about subscription options.pp. 119-129
by Kelly Heffner, David Tarditi, Michael D. Smith
Software Track (Session 4): Optimizations
Language and Virtual Machine Support for Efficient Fine-Grained Futures in JavaFull-text access may be available. Sign in or learn about subscription options.pp. 130-139
by Lingli Zhang, Chandra Krintz, Priya Nagpurkar
Software Track (Session 4): Optimizations
Call-chain Software Instruction Prefetching in J2EE Server ApplicationsFull-text access may be available. Sign in or learn about subscription options.pp. 140-149
by Priya Nagpurkar, Harold W. Cain, Mauricio Serrano, Jong-Deok Choi, Chandra Krintz
Software Track (Session 4): Optimizations
Detecting Change in Program Behavior for Adaptive OptimizationFull-text access may be available. Sign in or learn about subscription options.pp. 150-162
by Nitzan Peleg, Bilha Mendelson
Hardware Track (Session 5): Saving Energy
Reducing Energy Consumption of On-Chip Networks Through a Hybrid Compiler-Runtime ApproachFull-text access may be available. Sign in or learn about subscription options.pp. 163-174
by Guangyu Chen, Feihui Li, Mahmut Kandemir
Hardware Track (Session 5): Saving Energy
An Energy Efficient Parallel Architecture Using Near Threshold OperationFull-text access may be available. Sign in or learn about subscription options.pp. 175-188
by Ronald G. Dreslinkski, Bo Zhai, Trevor Mudge, David Blaauw, Dennis Sylvester
CIGAR: Application Partitioning for a CPU/Coprocessor ArchitectureFull-text access may be available. Sign in or learn about subscription options.pp. 317-326
by John H. Kelm, Isaac Gelado, Mark J. Murphy, Nacho Navarro, Steve Lumetta, Wen-mei Hwu
Software Track (Session 6): Algorithms
AA-Sort: A New Parallel Sorting Algorithm for Multi-Core SIMD ProcessorsFull-text access may be available. Sign in or learn about subscription options.pp. 189-198
by Hiroshi Inoue, Takao Moriyama, Hideaki Komatsu, Toshio Nakatani
Software Track (Session 6): Algorithms
The Fault Tolerant Parallel Algorithm: the Parallel Recomputing Based Failure RecoveryFull-text access may be available. Sign in or learn about subscription options.pp. 199-212
by Xuejun Yang, Yunfei Du, Panfeng Wang, Hongyi Fu, Jia Jia, Zhiyuan Wang, Guang Suo
Hardware Track (Session 7): Processors
Paceline: Improving Single-Thread Performance in Nanoscale CMPs through Core OverclockingFull-text access may be available. Sign in or learn about subscription options.pp. 213-224
by Brian Greskamp, Josep Torrellas
Hardware Track (Session 7): Processors
Early Register Release for Out-of-Order Processors with RegisterWindowsFull-text access may be available. Sign in or learn about subscription options.pp. 225-234
by Eduardo Quinones, Joan-Manuel Parcerisa, Antonio Gonzalez
Hardware Track (Session 7): Processors
L1 Cache Filtering Through Random Selection of Memory ReferencesFull-text access may be available. Sign in or learn about subscription options.pp. 235-244
by Yoav Etsion, Dror G. Feitelson
Hardware Track (Session 7): Processors
Effective Management of DRAM Bandwidth in Multicore ProcessorsFull-text access may be available. Sign in or learn about subscription options.pp. 245-258
by Nauman Rafique, Won-Taek Lim, Mithuna Thottethodi
Software Track (Session 8): Compilers
A Loop Correlation Technique to Improve Performance AuditingFull-text access may be available. Sign in or learn about subscription options.pp. 259-269
by Jeremy Lau, Matthew Arnold, Michael Hind, Brad Calder
Software Track (Session 8): Compilers
Latency Hiding in Multi-Threading and Multi-Processing of Network ApplicationsFull-text access may be available. Sign in or learn about subscription options.pp. 270-279
by Xiaofeng Guo, Jinquan Dai, Long Li, Zhiyuan Lv, Prashant R. Chandra
Software Track (Session 8): Compilers
Introducing Control Flow into Vectorized CodeFull-text access may be available. Sign in or learn about subscription options.pp. 280-291
by Jaewook Shin
Software Track (Session 8): Compilers
Automatic Correction of Loop TransformationsFull-text access may be available. Sign in or learn about subscription options.pp. 292-304
by Nicolas Vasilache, Albert Cohen, Louis-Noel Pouchet
Hardware Track (Session 9): Modeling & Measurement
FAME: FAirly MEasuring Multithreaded ArchitecturesFull-text access may be available. Sign in or learn about subscription options.pp. 305-316
by Javier Vera, Francisco J. Cazorla, Alex Pajuelo, Oliverio J. Santana, Enrique Fernandez, Mateo Valero
Hardware Track (Session 9): Modeling & Measurement
Using PredictiveModeling for Cross-Program Design Space Exploration in Multicore SystemsFull-text access may be available. Sign in or learn about subscription options.pp. 327-338
by Salman Khan, Polychronis Xekalakis, John Cavazos, Marcelo Cintra
Hardware Track (Session 9): Modeling & Measurement
CacheScouts: Fine-Grain Monitoring of Shared Caches in CMP PlatformsFull-text access may be available. Sign in or learn about subscription options.pp. 339-352
by Li Zhao, Ravi Iyer, Ramesh Illikkal, Jaideep Moses, Srihari Makineni, Don Newell
Software Track (Session 10): Transactional Memory & Locks
Component-Based Lock AllocationFull-text access may be available. Sign in or learn about subscription options.pp. 353-364
by Richard L. Halpert, Christopher J.F. Pickett, Clark Verbrugge
Notice of Violation of IEEE Publication Principles: A New Parallel Gauss-Seidel Method by Iteration Space Alternate TilingFull-text access may be available. Sign in or learn about subscription options.pp. 410-410
by Changjun Hu, Jilin Zhang, Jue Wang, Jianjiang Li, Liang Ding
Software Track (Session 10): Transactional Memory & Locks
JudoSTM: A Dynamic Binary-Rewriting Approach to Software Transactional MemoryFull-text access may be available. Sign in or learn about subscription options.pp. 365-375
by Marek Olszewski, Jeremy Cutler, J. Gregory Steffan
Software Track (Session 10): Transactional Memory & Locks
The OpenTM Transactional Application Programming InterfaceFull-text access may be available. Sign in or learn about subscription options.pp. 376-387
by Woongki Baek, Chi Cao Minh, Martin Trautmann, Christos Kozyrakis, Kunle Olukotun
Software Track (Session 10): Transactional Memory & Locks
A Study of a Transactional Parallel Routing AlgorithmFull-text access may be available. Sign in or learn about subscription options.pp. 388-398
by Ian Watson, Chris Kirkham, Mikel Luj?
Poster Abstracts
Ring Prediction for Non-Uniform Cache ArchitecturesFull-text access may be available. Sign in or learn about subscription options.pp. 401
by Sayaka Akioka, Feihui Li, Mahmut Kandemir, Padma Raghavan, Mary Jane Irwin
Poster Abstracts
Source Level Merging of Independent ProgramsFull-text access may be available. Sign in or learn about subscription options.pp. 402
by Yosi Ben Asher, Moshe Yuda
Poster Abstracts
Studying the impact of synchronization frequency on scheduling tasks with dependencies in heterogeneous systemsFull-text access may be available. Sign in or learn about subscription options.pp. 403
by F.M. Ciorba, I. Riakiotakis, G. Papakonstantinou, T. Andronikos, A.T. Chronopoulos
Poster Abstracts
Fast prototyping of complex Signal and Image Processing applications on SoC using homogenous network of communicating processorsFull-text access may be available. Sign in or learn about subscription options.pp. 404
by Lionel Damez, Jean Pierre Derutin
Poster Abstracts
Stream Scheduling: A Framework to Manage Bulk Operations in a Memory HierarchyFull-text access may be available. Sign in or learn about subscription options.pp. 405
by Abhishek Das, William J. Dally
Poster Abstracts
Studying Compiler-Microarchitecture Interactions through Interval AnalysisFull-text access may be available. Sign in or learn about subscription options.pp. 406
by Stijn Eyerman, Lieven Eeckhout, James E. Smith
A Lightweight Model for Software Thread-Level Speculation (TLS)Full-text access may be available. Sign in or learn about subscription options.pp. 419
by Cosmin E. Oancea, Alan Mycroft
Poster Abstracts
FastForward for Efficient Pipeline ParallelismFull-text access may be available. Sign in or learn about subscription options.pp. 407
by John Giacomoni, Tipp Moseley, Manish Vachharajani
Poster Abstracts
The Automatic Transformation of Linked List Data StructuresFull-text access may be available. Sign in or learn about subscription options.pp. 408
by Sven Groot, Harmen L.A. van der Spek, Erwin M. Bakker, Harry A.G. Wijshoff
Poster Abstracts
Trace-based Automatic Padding for Locality Improvement with Correlative Data Visualization InterfaceFull-text access may be available. Sign in or learn about subscription options.pp. 409
by Marco Hobbel, Thomas Rauber, Carsten Scholtes
Dynamic Cache Placement with Two-level Mapping to Reduce Conflict MissesFull-text access may be available. Sign in or learn about subscription options.pp. 422-422
by Kaushik Rajan, R. Govindarajan, Bharadwaj Amrutur
Poster Abstracts
A New Parallel Gauss-Seidel Method by Iteration Space Alternate TilingFull-text access may be available. Sign in or learn about subscription options.pp. 410
by Changjun Hu, Jilin Zhang, Jue Wang, Jianjiang Li, Liang Ding
Poster Abstracts
Performance Portable Optimizations for Loops Containing Communication OperationsFull-text access may be available. Sign in or learn about subscription options.pp. 411
by Costin Iancu, Wei Chen, Katherine Yelick
Poster Abstracts
Exploring the Application Behavior Space Using Parameterized Synthetic BenchmarksFull-text access may be available. Sign in or learn about subscription options.pp. 412
by Ajay M. Joshi, Lieven Eeckhout, Lizy K. John
Poster Abstracts
Studying Asynchronous Shared Memory ComputationsFull-text access may be available. Sign in or learn about subscription options.pp. 413
by Simo Juvaste
Poster Abstracts
Fast Track: Supporting Unsafe Optimizations with Software SpeculationFull-text access may be available. Sign in or learn about subscription options.pp. 414
by Kirk Kelsey, Chengliang Zhang, Chen Ding
Poster Abstracts
Hybrid Specialization: A Trade-off Between Static and Dynamic SpecializationFull-text access may be available. Sign in or learn about subscription options.pp. 415
by Minhaj Ahmad Khan, Henri-Pierre Charles, Denis Barthou
Poster Abstracts
Rate-Driven Control of Resizable Caches for Highly Threaded SMT ProcessorsFull-text access may be available. Sign in or learn about subscription options.pp. 416
by Sonia Lopez, Steve Dropsho, David H. Albonesi, Oscar Garnica, Juan Lanchares
Poster Abstracts
Redesigning Parallel Symbolic Computations PackagesFull-text access may be available. Sign in or learn about subscription options.pp. 417
by Georgiana Macariu, Marc Frincu, Alexandru Carstea, Dana Petcu, Andrei Eckstein
Poster Abstracts
MLP-Aware Dynamic Cache PartitioningFull-text access may be available. Sign in or learn about subscription options.pp. 418
by Miquel Moreto, Francisco J. Cazorla, Alex Ramirez, Mateo Valero
A Scalable Low Power Store Queue for Large InstructionWindow ProcessorsFull-text access may be available. Sign in or learn about subscription options.pp. 430-430
by R. Vivekanandharn, R. Govindarajan
Poster Abstracts
A Lightweight Model for Software Thread-Level Speculation (TLS)Full-text access may be available. Sign in or learn about subscription options.pp. 419
by Cosmin E. Oancea, Alan Mycroft
Poster Abstracts
HelperCore_DB: Exploiting Multicore Technology for DatabasesFull-text access may be available. Sign in or learn about subscription options.pp. 420
by Kostas Papadopoulos, Kyriakos Stavrou, Pedro Trancoso
Poster Abstracts
Data Structure Exploration of Dynamic ApplicationsFull-text access may be available. Sign in or learn about subscription options.pp. 421
by L. Papadopoulos, C. Baloukas, D. Soudris, K. Potamianos, N. Voros
Poster Abstracts
Runahead Threads: Reducing Resource Contention in SMT ProcessorsFull-text access may be available. Sign in or learn about subscription options.pp. 423
by Tanausu Ramirez, Alex Pajuelo, Oliverio J. Santana, Mateo Valero
Poster Abstracts
Reducing the Impact of Process Variability with Prefetching and Criticality-Based Resource AllocationFull-text access may be available. Sign in or learn about subscription options.pp. 424
by Bogdan F. Romanescu, Michael E. Bauer, Daniel J. Sorin, Sule Ozev
Poster Abstracts
Drug Design on the Cell BroadBand EngineFull-text access may be available. Sign in or learn about subscription options.pp. 425
by Harald Servat, Cecilia Gonzalez, Xavier Aguilar, Daniel Cabrera, Daniel Jimenez
Poster Abstracts
Bridging Inputs and Program Dynamic BehaviorFull-text access may be available. Sign in or learn about subscription options.pp. 426
by Xipeng Shen, Feng Mao
Poster Abstracts
Power-Aware Compiler Controllable Chip MultiprocessorFull-text access may be available. Sign in or learn about subscription options.pp. 427
by Hiroaki Shikano, Jun Shirako, Yasutaka Wada, Keiji Kimura, Hironori Kasahara
Poster Abstracts
RSTM : A Relaxed Consistency Software Transactional Memory for MulticoresFull-text access may be available. Sign in or learn about subscription options.pp. 428
by Jaswanth Sreeram, Romain Cledat, Tushar Kumar, Santosh Pande
Poster Abstracts
VB-MT: Design Issues and Performance of the Validation Buffer Microarchitecture for Multithreaded ProcessorsFull-text access may be available. Sign in or learn about subscription options.pp. 429
by R. Ubal, J. Sahuquillo, S. Petit, P. Lopez, J. Duato
Poster Abstracts
Adapting to Intermittent Faults in Future Multicore SystemsFull-text access may be available. Sign in or learn about subscription options.pp. 431
by Philip M. Wells, Koushik Chakraborty, Gurindar S. Sohi
Poster Abstracts
A Phase-Adaptive Approach to Increasing Cache PerformanceFull-text access may be available. Sign in or learn about subscription options.pp. 432
by Matthew A. Watkins, Sally A. McKee, Lambert Schaelicke
Poster Abstracts
Compiler Optimizations for Fault Tolerance Software CheckingFull-text access may be available. Sign in or learn about subscription options.pp. 433
by Jing Yu, Maria Jesus Garzaran
Poster Abstracts
Optimizing Bandwidth Constraint through Register Interconnection for Stream ProcessorsFull-text access may be available. Sign in or learn about subscription options.pp. 434
by Weihua Zhang, Tao Bao, Binyu Zang, Chuanqi Zhu
Author Index
Author IndexFreely available from IEEE.pp. 435
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