1. Home
  2. Proceedings
  3. PACT
  4. PACT 2008
Default Cover Image

2008 International Conference on Parallel Architectures and Compilation Techniques (PACT)

Oct. 25 2008 to Oct. 29 2008

Toronto, ON, Canada

Table of Contents

Title pagesFull-text access may be available. Sign in or learn about subscription options.pp. c1-c1
GPU evolution: Will graphics morph into compute?Full-text access may be available. Sign in or learn about subscription options.pp. 1-1
by Norm Rubin
Outer-loop vectorization - revisited for short SIMD architecturesFull-text access may be available. Sign in or learn about subscription options.pp. 2-11
by Dorit Nuzman, Ayal Zaks
Redundancy elimination revisitedFull-text access may be available. Sign in or learn about subscription options.pp. 12-21
by Keith Cooper, Jason Eckhardt, Ken Kennedy
Exploiting loop-dependent Stream Reuse for stream processorsFull-text access may be available. Sign in or learn about subscription options.pp. 22-31
by Xuejun Yang, Ying Zhang, Jingling Xue, Ian Rogers, Gen Li, Guibin Wang
Feature selection and policy optimization for distributed instruction placement using reinforcement learningFull-text access may be available. Sign in or learn about subscription options.pp. 32-42
by Katherine E. Coons, Behnam Robatmili, Matthew E. Taylor, Betrand A. Maher, Doug Burger, Kathryn S. McKinley
Core Cannibalization Architecture: Improving lifetime chip performance for multicore processors in the presence of hard faultsFull-text access may be available. Sign in or learn about subscription options.pp. 43-51
by Bogdan F. Romanescu, Daniel J. Sorin
Pangaea: A tightly-coupled IA32 heterogeneous chip multiprocessorFull-text access may be available. Sign in or learn about subscription options.pp. 52-61
by Henry Wong, Anne Bracy, Ethan Schuchman, Tor M. Aamodt, Jamison D. Collins, Perry H. Wang, Gautham Chinya, Ankur Khandelwal Groen, Hong Jiang, Hong Wang
Skewed redundancyFull-text access may be available. Sign in or learn about subscription options.pp. 62-71
by Gordon B. Bell, Mikko H. Lipasti
The PARSEC benchmark suite: Characterization and architectural implicationsFull-text access may be available. Sign in or learn about subscription options.pp. 72-81
by Christian Bienia, Sanjeev Kumar, Jaswinder Pal Singh, Kai Li
Visualizing potential parallelism in sequential programsFull-text access may be available. Sign in or learn about subscription options.pp. 82-90
by Graham D. Price, John Giacomoni, Manish Vachharajani
Characterizing and modeling the behavior of context switch misses!Full-text access may be available. Sign in or learn about subscription options.pp. 91-101
by Fang Liu, Fei Guo, Yan Solihin, Seongbeom Kim, Abdulaziz Eker
MCAMP: Communication optimization on Massively Parallel Machines with hierarchical scratch-pad memoryFull-text access may be available. Sign in or learn about subscription options.pp. 102-111
by Hiroshige Hayashizaki, Yutaka Sugawara, Mary Inaba, Kei Hiraki
Profiler and compiler assisted adaptive I/O prefetching for shared storage cachesFull-text access may be available. Sign in or learn about subscription options.pp. 112-121
by Seung Woo Son, Sai Prashanth Muralidhara, Ozcan Ozturk, Mahmut Kandemir, Ibrahim Kolcu, Mustafa Karakoy
Runtime optimization of vector operations on large scale SMP clustersFull-text access may be available. Sign in or learn about subscription options.pp. 122-132
by Costin Iancu, Steven Hofmeyr
(How) can programmers conquer the multicore menace?Full-text access may be available. Sign in or learn about subscription options.pp. 133-133
by Saman Amarasinghe
Distributed Cooperative CachingFull-text access may be available. Sign in or learn about subscription options.pp. 134-143
by Enric Herrero, José González, Ramon Canal
Scalable and reliable communication for hardware transactional memoryFull-text access may be available. Sign in or learn about subscription options.pp. 144-154
by Seth H. Pugsley, Manu Awasthi, Niti Madan, Naveen Muralimanohar, Rajeev Balasubramonian
Improving support for locality and fine-grain sharing in chip multiprocessorsFull-text access may be available. Sign in or learn about subscription options.pp. 155-165
by Hemayet Hossain, Sandhya Dwarkadas, Michael C. Huang
Edge-centric modulo scheduling for coarse-grained reconfigurable architecturesFull-text access may be available. Sign in or learn about subscription options.pp. 166-176
by Hyunchul Park, Kevin Fan, Scott Mahlke, Taewook Oh, Heeseok Kim, Hong-seok Kim
Multi-Optimization power management for chip multiprocessorsFull-text access may be available. Sign in or learn about subscription options.pp. 177-186
by Ke Meng, Russ Joseph, Robert P. Dick, Li Shang
Multitasking workload scheduling on flexible-core chip multiprocessorsFull-text access may be available. Sign in or learn about subscription options.pp. 187-196
by Divya P. Gulati, Changkyu Kim, Simha Sethumadhavan, Stephen W. Keckler, Doug Burger
Leveraging on-chip networks for data cache migration in chip multiprocessorsFull-text access may be available. Sign in or learn about subscription options.pp. 197-207
by Noel Eisley, Li-Shiuan Peh, Li Shang
Adaptive insertion policies for managing shared cachesFull-text access may be available. Sign in or learn about subscription options.pp. 208-219
by Aamer Jaleel, William Hasenplaugh, Moinuddin Qureshi, Julien Sebot, Simon Steely, Joel Emer
Analysis and approximation of optimal co-scheduling on Chip MultiprocessorsFull-text access may be available. Sign in or learn about subscription options.pp. 220-229
by Yunlian Jiang, Xipeng Shen, Chen Jie, Rahul Tripathi
An Adaptive Resource Partitioning Algorithm for SMT processorsFull-text access may be available. Sign in or learn about subscription options.pp. 230-239
by Huaping Wang, Israel Koren, C. Mani Krishna
Meeting points: Using thread criticality to adapt multicore hardware to parallel regionsFull-text access may be available. Sign in or learn about subscription options.pp. 240-249
by Qiong Cai, José González, Ryan Rakvic, Grigorios Magklis, Pedro Chaparro, Antonio González
Prediction models for multi-dimensional power-performance optimization on many coresFull-text access may be available. Sign in or learn about subscription options.pp. 250-259
by Matthew Curtis-Maury, Ankur Shah, Filip Blagojevic, Dimitrios S. Nikolopoulos, Bronis R. de Supinski, Martin Schulz
Mars: A MapReduce Framework on graphics processorsFull-text access may be available. Sign in or learn about subscription options.pp. 260-269
by Bingsheng He, Wenbin Fang, Qiong Luo, Naga K. Govindaraju, Tuyong Wang
Multi-mode energy management for multi-tier server clustersFull-text access may be available. Sign in or learn about subscription options.pp. 270-279
by Tibor Horvath, Kevin Skadron
A tuning framework for software-managed memory hierarchiesFull-text access may be available. Sign in or learn about subscription options.pp. 280-291
by Manman Ren, Ji Young Park, Mike Houston, Alex Aiken, William J. Dally
Hybrid access-specific software cache techniques for the cell BE architectureFull-text access may be available. Sign in or learn about subscription options.pp. 292-302
by Marc Gonzàlez, Nikola Vujic, Xavier Martorell, Eduard Ayguadé, Alexandre E. Eichenberger, Tong Chen, Zehra Sura, Tao Zhang, Kevin O'Brien, Kathryn O'Brien
COMIC: A coherent shared memory interface for cell BEFull-text access may be available. Sign in or learn about subscription options.pp. 303-314
by Jaejin Lee, Sangmin Seo, Chihun Kim, Junghyun Kim, Posung Chun, Zehra Sura, Jungwon Kim, SangYong Han
Author indexFreely available from IEEE.pp. 315-315
Showing 34 out of 34