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2012 21st International Conference on Parallel Architectures and Compilation Techniques (PACT)

Sept. 19 2012 to Sept. 23 2012

Minneapolis, MN, USA

Table of Contents

[Front matter]Freely available from IEEE.pp. c1-c1
The changing role of supercomputingFreely available from IEEE.pp. 1-1
by Peter J. Ungaro
Power-aware multi-core simulation for early design stage hardware/software co-optimizationFull-text access may be available. Sign in or learn about subscription options.pp. 3-12
by Wim Heirman, Souradip Sarkar, Trevor E. Carlson, Ibrahim Hur, Lieven Eeckhout
PGCapping: Exploiting power gating for power capping and core lifetime balancing in CMPsFull-text access may be available. Sign in or learn about subscription options.pp. 13-22
by Kai Ma, Xiaorui Wang
Power-efficient time-sensitive mapping in heterogeneous systemsFull-text access may be available. Sign in or learn about subscription options.pp. 23-32
by Cong Liu, Jian Li, Wei Huang, Juan Rubio, Evan Speight, Felix Xiaozhu Lin
Fast and efficient automatic memory management for GPUs using compiler-assisted runtime coherence schemeFull-text access may be available. Sign in or learn about subscription options.pp. 33-42
by Sreepathi Pai, R. Govindarajan, Matthew J. Thazhuthaveetil
Riposte: A trace-driven compiler and parallel VM for vector code in RFull-text access may be available. Sign in or learn about subscription options.pp. 43-51
by Justin Talbot, Zachary DeVito, Pat Hanrahan
Auto-parallelizing stateful distributed streaming applicationsFull-text access may be available. Sign in or learn about subscription options.pp. 53-64
by Scott Schneider, Martin Hirzel, Bugra Gedik, Kun-Lung Wu
PEPON: Performance-aware hierarchical power budgeting for NoC based multicoresFull-text access may be available. Sign in or learn about subscription options.pp. 65-74
by Akbar Sharifi, Asit K. Mishra, Shekhar Srikantaiah, Mahmut Kandemir, Chita R. Das
XPoint cache: Scaling existing bus-based coherence protocols for 2D and 3D many-core systemsFull-text access may be available. Sign in or learn about subscription options.pp. 75-85
by Ronald G. Dreslinski, Thomas Manville, Korey Sewell, Reetuparna Das, Nathaniel Pinckney, Sudhir Satpathy, David Blaauw, Dennis Sylvester, Trevor Mudge
APCR: An adaptive physical channel regulator for On-Chip InterconnectsFull-text access may be available. Sign in or learn about subscription options.pp. 87-96
by Lei Wang, Poornachandran Kumar, Ki Hwan Yum, Eun Jung Kim
Pointy: A hybrid pointer prefetcher for managed runtime systemsFull-text access may be available. Sign in or learn about subscription options.pp. 97-106
by Ioana Burcea, Livio Soares, Andreas Moshovos
Scalability-based manycore partitioningFull-text access may be available. Sign in or learn about subscription options.pp. 107-116
by Hiroshi Sasaki, Teruo Tanimoto, Koji Inoue, Hiroshi Nakamura
Optimizing datacenter power with memory system levers for guaranteed Quality-of-ServiceFull-text access may be available. Sign in or learn about subscription options.pp. 117-126
by Kshitij Sudan, Sadagopan Srinivasan, Rajeev Balasubramonian, Ravi Iyer
Evaluation of Blue Gene/Q hardware support for transactional memoriesFull-text access may be available. Sign in or learn about subscription options.pp. 127-136
by Amy Wang, Matthew Gaudet, Peng Wu, José Nelson Amaral, Martin Ohmacht, Christopher Barton, Raul Silvera, Maged Michael
Making data prefetch smarter: Adaptive prefetching on POWER7Full-text access may be available. Sign in or learn about subscription options.pp. 137-146
by Víctor Jiménez, Roberto Gioiosa, Francisco J. Cazorla, Alper Buyuktosunoglu, Pradip Bose, Francis P. O'Connell
Enhancing performance optimization of multicore chips and multichip nodes with data structure metricsFull-text access may be available. Sign in or learn about subscription options.pp. 147-156
by Ashay Rane, James Browne
Compiling to avoid communicationFull-text access may be available. Sign in or learn about subscription options.pp. 157-157
by Kathy Yelick
Visualizing transactional memoryFull-text access may be available. Sign in or learn about subscription options.pp. 159-170
by Justin E. Gottschlich, Maurice P. Herlihy, Gilles A. Pokam, Jeremy G. Siek
Sandboxing transactional memoryFull-text access may be available. Sign in or learn about subscription options.pp. 171-179
by Luke Dalessandro, Michael L. Scott
Transactional prefetching: Narrowing the window of contention in Hardware Transactional MemoryFull-text access may be available. Sign in or learn about subscription options.pp. 181-190
by Anurag Negi, Adrià Armejach, Adrián Cristal, Osman S. Unsal, Per Stenstrom
RISE: Improving the streaming processors reliability against soft errors in GPGPUsFull-text access may be available. Sign in or learn about subscription options.pp. 191-200
by Jingweijia Tan, Xin Fu
Chrysalis analysis: Incorporating synchronization arcs in dataflow-analysis-based parallel monitoringFull-text access may be available. Sign in or learn about subscription options.pp. 201-212
by Michelle L. Goodstein, Shimin Chen, Phillip B. Gibbons, Michael A. Kozuch, Todd C. Mowry
Probabilistic diagnosis of performance faults in large-scale parallel applicationsFull-text access may be available. Sign in or learn about subscription options.pp. 213-222
by Ignacio Laguna, Dong H. Ahn, Bronis R. de Supinski, Saurabh Bagchi, Todd Gamblin
Top500 versus sustained performance - the top problems with the TOP500 list - and what to do about themFull-text access may be available. Sign in or learn about subscription options.pp. 223-230
by William Kramer
Practically Private: Enabling high performance CMPs through compiler-assisted data classificationFull-text access may be available. Sign in or learn about subscription options.pp. 231-240
by Yong Li, Rami Melhem, Alex K. Jones
Complexity-effective multicore coherenceFull-text access may be available. Sign in or learn about subscription options.pp. 241-251
by Alberto Ros, Stefanos Kaxiras
HaLock: Hardware-assisted lock contention detection in multithreaded applicationsFull-text access may be available. Sign in or learn about subscription options.pp. 253-262
by Yongbing Huang, Zehan Cui, Licheng Chen, Wenli Zhang, Yungang Bao, Mingyu Chen
Runtime detection and optimization of collective communication patternsFull-text access may be available. Sign in or learn about subscription options.pp. 263-272
by Torsten Hoefler, Timo Schneider
Coalition Threading: Combining traditional and non-traditional parallelism to maximize scalabilityFull-text access may be available. Sign in or learn about subscription options.pp. 273-282
by Md Kamruzzaman, Steven Swanson, Dean M. Tullsen
Shared memory multiplexing: A novel way to improve GPGPU throughputFull-text access may be available. Sign in or learn about subscription options.pp. 283-292
by Yi Yang, Ping Xiang, Mike Mantor, Norm Rubin, Huiyang Zhou
Introducing Hierarchy-awareness in replacement and bypass algorithms for last-level cachesFull-text access may be available. Sign in or learn about subscription options.pp. 293-304
by Mainak Chaudhuri, Jayesh Gaur, Nithiyanandan Bashyam, Sreenivas Subramoney, Joseph Nuzman
Efficient techniques for predicting cache sharing and throughputFull-text access may be available. Sign in or learn about subscription options.pp. 305-314
by Andreas Sandberg, David Black-Schaffer, Erik Hagersten
Optimal bypass monitor for high performance last-level cachesFull-text access may be available. Sign in or learn about subscription options.pp. 315-324
by Lingda Li, Dong Tong, Zichao Xie, Junlin Lu, Xu Cheng
Lossless and lossy memory I/O link compression for improving performance of GPGPU workloadsFull-text access may be available. Sign in or learn about subscription options.pp. 325-334
by Vijay Sathish, Michael J. Schulte, Nam Sung Kim
Multi2Sim: A simulation framework for CPU-GPU computingFull-text access may be available. Sign in or learn about subscription options.pp. 335-344
by Rafael Ubal, Byunghyun Jang, Perhaad Mistry, Dana Schaa, David Kaeli
A yoke of oxen and a thousand chickens for heavy lifting graph processingFull-text access may be available. Sign in or learn about subscription options.pp. 345-354
by Abdullah Gharaibeh, Lauro Beltrão Costa, Elizeu Santos-Neto, Matei Ripeanu
The evicted-address filter: A unified mechanism to address both cache pollution and thrashingFull-text access may be available. Sign in or learn about subscription options.pp. 355-366
by Vivek Seshadri, Onur Mutlu, Michael A Kozuch, Todd C Mowry
A software memory partition approach for eliminating bank-level interference in multicore systemsFull-text access may be available. Sign in or learn about subscription options.pp. 367-375
by Lei Liu, Zehan Cui, Mingjie Xing, Yungang Bao, Mingyu Chen, Chengyong Wu
Base-delta-immediate compression: Practical data compression for on-chip cachesFull-text access may be available. Sign in or learn about subscription options.pp. 377-388
by Gennady Pekhimenko, Vivek Seshadri, Onur Mutlu, Michael A. Kozuch, Phillip B. Gibbons, Todd C. Mowry
Hardware acceleration in the IBM PowerEN processor: architecture and performanceFull-text access may be available. Sign in or learn about subscription options.pp. 389-399
by Anil Krishna, Timothy Heil, Nicholas Lindberg, Farnaz Toussi, Steven VanderWiel
Workload and power budget partitioning for single-chip heterogeneous processorsFull-text access may be available. Sign in or learn about subscription options.pp. 401-410
by Hao Wang, Vijay Sathish, Ripudaman Singh, Michael J. Schulte, Nam Sung Kim
Database analytics acceleration using FPGAsFull-text access may be available. Sign in or learn about subscription options.pp. 411-420
by Bharat Sukhwani, Hong Min, Mathew Thoennes, Parijat Dube, Balakrishna Iyer, Bernard Brezzo, Donna Dillenberger, Sameh Asaad
LumiNOC: A power-efficient, high-performance, photonic network-on-chip for future parallel architecturesFull-text access may be available. Sign in or learn about subscription options.pp. 421-422
by Cheng Li, Mark Browning, Paul V. Gratz, Samuel Palermo
Acceleration of bulk memory operations in a heterogeneous multicore architectureFull-text access may be available. Sign in or learn about subscription options.pp. 423-424
by JongHyuk Lee, Ziyi Liu, Xiaonan Tian, Dong Hyuk Woo, Weidong Shi, Dainis Boumber
Integrating nanophotonics in GPU microarchitectureFull-text access may be available. Sign in or learn about subscription options.pp. 425-426
by Nilanjan Goswami, Zhongqi Li, Ajit Verma, Ramkumar Shankar, Tao Li
Branch and data herding: Reducing control and memory divergence for error-tolerant GPU applicationsFull-text access may be available. Sign in or learn about subscription options.pp. 427-428
by John Sartori, Rakesh Kumar
Layout-oblivious optimization for matrix computationsFull-text access may be available. Sign in or learn about subscription options.pp. 429-430
by Huimin Cui, Qing Yi, Jingling Xue, Xiaobing Feng
Boost.SIMD: Generic programming for portable SIMDizationFull-text access may be available. Sign in or learn about subscription options.pp. 431-432
by Pierre Estérie, Mathias Gaunard, Joel Falcou, Jean-Thierry Lapresté, Brigitte Rozoy
Speculative parallelization needs rigorFull-text access may be available. Sign in or learn about subscription options.pp. 433-434
by Zhijia Zhao, Bo Wu, Xipeng Shen
Supporting stateful tasks in a dataflow graphFull-text access may be available. Sign in or learn about subscription options.pp. 435-436
by Vladimir Gajinov, Srdjan Stipic, Osman S. Unsal, Tim Harris, Eduard Ayguadé, Adrián Cristal
MaSiF: Machine learning guided auto-tuning of Parallel SkeletonsFull-text access may be available. Sign in or learn about subscription options.pp. 437-438
by Alexander Collins, Christian Fensch, Hugh Leather
TMNOC: A case of HTM and NoC Co-design for increased energy efficiency and concurrencyFull-text access may be available. Sign in or learn about subscription options.pp. 439-440
by Lihang Zhao, Woojin Choi, Jeff Draper
Application-aware prefetch prioritization in on-chip networksFull-text access may be available. Sign in or learn about subscription options.pp. 441-442
by Nachiappan Chidambaram Nachiappan, Asit K. Mishra, Mahmut Kandemir, Anand Sivasubramaniam, Onur Mutlu, Chita R. Das
ReCaP: A Region-Based cure for the common cold cacheFull-text access may be available. Sign in or learn about subscription options.pp. 443-444
by Jason Zebchuk, Harold W. Cain, Vijayalakshmi Srinivasan, Andreas Moshovos
Power-efficient computing for compute-intensive GPGPU applicationsFull-text access may be available. Sign in or learn about subscription options.pp. 445-446
by Syed Zohaib Gilani, Nam Sung Kim, Michael Schulte
Off-chip access localization for NoC-based multicoresFull-text access may be available. Sign in or learn about subscription options.pp. 447-448
by Wei Ding, Mahmut Kandemir, Yuanrui Zhang, Emre Kultursay
Many-thread aware instruction-level parallelism: Architecting shader cores for GPU computingFull-text access may be available. Sign in or learn about subscription options.pp. 449-450
by Ping Xiang, Yi Yang, Mike Mantor, Norm Rubin, Huiyang Zhou
PS-Dir: A scalable two-level directory cacheFull-text access may be available. Sign in or learn about subscription options.pp. 451-452
by Joan J. Valls, Alberto Ros, Julio Sahuquillo, María E. Gómez, José Duato
Inference and declaration of independence: Impact on deterministic task parallelismFull-text access may be available. Sign in or learn about subscription options.pp. 453-454
by Foivos S. Zakkak, Dimitrios Chasapis, Polyvios Pratikakis, Angelos Bilas, Dimitrios S. Nikolopoulos
Application-to-core mapping policies to reduce memory interference in multi-core systemsFull-text access may be available. Sign in or learn about subscription options.pp. 455-456
by Reetuparna Das, Rachata Ausavarungnirun, Onur Mutlu, Akhilesh Kumar, Mani Azimi
Bandwidth Bandit: Quantitative characterization of memory contentionFull-text access may be available. Sign in or learn about subscription options.pp. 457-458
by David Eklov, Nikos Nikoleris, David Black-Schaffer, Erik Hagersten
Speculative dynamic vectorization for HW/SW codesigned processorsFull-text access may be available. Sign in or learn about subscription options.pp. 459-460
by Rakesh Kumar, Alejandro Martínez, Antonio González
Fine-grained parallel traversals of irregular data structuresFull-text access may be available. Sign in or learn about subscription options.pp. 461-462
by Bin Ren, Gagan Agrawal, James R. Larus, Todd Mytkowicz, Tomi Poutanen, Wolfram Schulte
High-performance analysis of filtered semantic graphsFull-text access may be available. Sign in or learn about subscription options.pp. 463-464
by Aydin Buluç, Armando Fox, John R. Gilbert, Shoaib Kamil, Adam Lugowski, Leonid Oliker, Samuel Williams
Energy-efficient cache partitioning for future CMPsFull-text access may be available. Sign in or learn about subscription options.pp. 465-466
by Karthik T. Sundararajan, Timothy M. Jones, Nigel P. Topham
A low-overhead dynamic optimization framework for multicoresFull-text access may be available. Sign in or learn about subscription options.pp. 467-468
by Christopher W. Fletcher, Rachael Harding, Omer Khan, Srinivas Devadas
Making it practical and effective: Fast and precise May-Happen-in-Parallel analysisFull-text access may be available. Sign in or learn about subscription options.pp. 469-470
by Congming Chen, Wei Huo, Xiaobing Feng
Mileage-based Contention Management in Transactional MemoryFull-text access may be available. Sign in or learn about subscription options.pp. 471-471
by Woojin Choi, Lihang Zhao, Jeff Draper
System-level power-performance efficiency modeling for emergent GPU architecturesFull-text access may be available. Sign in or learn about subscription options.pp. 473-473
by Shuaiwen Song, Kirk W. Cameron
Transactional event profiling in a best-effort hardware transactional memory systemFull-text access may be available. Sign in or learn about subscription options.pp. 475-475
by Matthew Gaudet, Josè Nelson Amaral
Transparent runtime deadlock eliminationFull-text access may be available. Sign in or learn about subscription options.pp. 477-477
by Hari. K. Pyla, Srinidhi Varadarajan
Design of a storage processing unitFull-text access may be available. Sign in or learn about subscription options.pp. 479-479
by Peng Li, Kevin Gomez, David J. Lilja
SkipCache: Miss-rate aware cache managementFull-text access may be available. Sign in or learn about subscription options.pp. 481-481
by Raghavendra K, Tripti S Warrier, Madhu Mutyam
Using combined profiling to decide when Thread Level Speculation is profitableFull-text access may be available. Sign in or learn about subscription options.pp. 483-483
by Arnamoy Bhattacharyya
Hardware prefetchers for emerging parallel applicationsFull-text access may be available. Sign in or learn about subscription options.pp. 485-485
by Biswabandan Panda, Shankar Balachandran
Strategies based on green policies to the grid resource allocationFull-text access may be available. Sign in or learn about subscription options.pp. 487-487
by Fábio Coutinho, Luís Alfredo V. de Carvalho
Linearly compressed pages: A main memory compression framework with low complexity and low latencyFull-text access may be available. Sign in or learn about subscription options.pp. 489-489
by Gennady Pekhimenko, Todd C. Mowry, Onur Mutlu
Energy-efficient workload mapping in heterogeneous systems with multiple types of resourcesFull-text access may be available. Sign in or learn about subscription options.pp. 491-491
by Cong Liu
Phase-based scheduling and thread migration for heterogeneous multicore processorsFull-text access may be available. Sign in or learn about subscription options.pp. 493-493
by Lina Sawalha, Ronald D. Barnes
Author indexFreely available from IEEE.pp. 495-496
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