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Proceedings Seventeenth IEEE International Workshop on Rapid System Prototyping

June 14 2006 to June 16 2006

Chania, Crete

Table of Contents

Introduction
Message from the General ChairsFreely available from IEEE.pp. viii
Introduction
Message from the Organizing ChairFreely available from IEEE.pp. ix
Introduction
Message from the Program ChairsFreely available from IEEE.pp. x
Introduction
AcknowledgmentsFreely available from IEEE.pp. xi
Introduction
Conference CommitteesFreely available from IEEE.pp. xii
Session 1: Software Verification
Dynamic Mapping of Runtime Information Models for Debugging Embedded SoftwareFull-text access may be available. Sign in or learn about subscription options.pp. 3-9
Session 1: Software Verification
Principles for System Prototype and Verification Using Metamodel Based TransformationsFull-text access may be available. Sign in or learn about subscription options.pp. 10-17
Session 1: Software Verification
Creation and Validation of Embedded Assertion StatechartsFull-text access may be available. Sign in or learn about subscription options.pp. 17-23
Session 1: Software Verification
Early Embedded Software Design Space Exploration Using UML-Based EstimationFull-text access may be available. Sign in or learn about subscription options.pp. 24-32
Session 2: Hardware Performance Estimation
A Prototyping Tool for Analysis and Modeling of Video Transmission Traces over IP NetworksFull-text access may be available. Sign in or learn about subscription options.pp. 33-39
Session 2: Hardware Performance Estimation
Rapid Resource-Constrained Hardware Performance EstimationFull-text access may be available. Sign in or learn about subscription options.pp. 40-46
Session 2: Hardware Performance Estimation
Rapid Performance and Power Consumption Estimation Methods for Embedded System DesignFull-text access may be available. Sign in or learn about subscription options.pp. 47-53
Session 2: Hardware Performance Estimation
Performance Evaluation of an Adaptive FPGA for Network ApplicationsFull-text access may be available. Sign in or learn about subscription options.pp. 54-62
Session 3: Design Methodologies
A Mixed-Level Virtual Prototyping Environment for Refinement-Based Design EnvironmentFull-text access may be available. Sign in or learn about subscription options.pp. 63-68
Session 3: Design Methodologies
The Prototyping Methodology of a Data Receiver for Digital Audio Broadcasting (DAB) NetworksFull-text access may be available. Sign in or learn about subscription options.pp. 76-81
Session 3: Design Methodologies
System-on-Chip Design Methodology for a Statistical CoderFull-text access may be available. Sign in or learn about subscription options.pp. 82-90
Session 4: Hardwared Verification
Introspection Mechanisms for Semi-Formal Verification in a System-Level Design EnvironmentFull-text access may be available. Sign in or learn about subscription options.pp. 91-97
Session 4: Hardwared Verification
Asynchronous Assertion Monitors for multi-Clock Domain System VerificationFull-text access may be available. Sign in or learn about subscription options.pp. 98-102
Session 4: Hardwared Verification
Formalizing the Incremental Design and Verification Process of a Pipelined Protocol ConverterFull-text access may be available. Sign in or learn about subscription options.pp. 103-109
Development of an FPGA-based System for Real-Time Simulation of Photovoltaic ModulesFull-text access may be available. Sign in or learn about subscription options.pp. 200-208
Session 4: Hardwared Verification
Integrated Verification Approach during ADL-Driven Processor DesignFull-text access may be available. Sign in or learn about subscription options.pp. 110-118
Session 5: Software Prototyping Methodologies
Wcomp: a Multi-Design Approach for Prototyping Applications using Heterogeneous ResourcesFull-text access may be available. Sign in or learn about subscription options.pp. 119-125
Session 5: Software Prototyping Methodologies
An Agile BSP Modeling Methodology: Cross Platform BSP Framework (CPBF)Full-text access may be available. Sign in or learn about subscription options.pp. 126-132
Session 5: Software Prototyping Methodologies
A Case Study of Design Space Exploration for Embedded Multimedia Applications on SoCsFull-text access may be available. Sign in or learn about subscription options.pp. 133-139
Session 5: Software Prototyping Methodologies
Generative Business Process Prototyping FrameworkFull-text access may be available. Sign in or learn about subscription options.pp. 140-148
Session 6: Co-Design
An Embedded Java Virtual Machine Using Network-on-Chip DesignFull-text access may be available. Sign in or learn about subscription options.pp. 149-155
Session 6: Co-Design
Service Based Component Design Approach for Flexible Hardware/Software Interface ModelingFull-text access may be available. Sign in or learn about subscription options.pp. 156-162
Session 6: Co-Design
RTOS Scheduler Implementation in Hardware and Software for Real Time ApplicationsFull-text access may be available. Sign in or learn about subscription options.pp. 163-168
Session 6: Co-Design
Application-Level Memory Optimization for MPSoCFull-text access may be available. Sign in or learn about subscription options.pp. 169-178
Session 7: Advanced Simulation Techniques
Platform Development for Run-Time Reconfigurable Co-EmulationFull-text access may be available. Sign in or learn about subscription options.pp. 179-185
Session 7: Advanced Simulation Techniques
Formal Definitions of Simulation Interfaces in a Continuous/Discrete Co-Simulation ToolFull-text access may be available. Sign in or learn about subscription options.pp. 186-192
Session 7: Advanced Simulation Techniques
Rapid Prototyping Design Acceleration Using a Novel Merging Methodology for Partial Configuration Streams of Xilinx Virtex-II FPGAsFull-text access may be available. Sign in or learn about subscription options.pp. 193-199
Session 7: Advanced Simulation Techniques
Development of an FPGA-based System for Real-Time Simulation ofFull-text access may be available. Sign in or learn about subscription options.pp. 200-208
Session 8: Hardwared Implementation
Parameter-Specific FPGA Implementation of Edit-Distance CalculationFull-text access may be available. Sign in or learn about subscription options.pp. 209-215
Session 8: Hardwared Implementation
A High Performance Parallel FIR Filters Generation ToolFull-text access may be available. Sign in or learn about subscription options.pp. 216-222
Session 8: Hardwared Implementation
Rapid Phototyping of a System-on-a-Chip for the BLAST Algorithm ImplementationFull-text access may be available. Sign in or learn about subscription options.pp. 223-229
Session 8: Hardwared Implementation
Design and Implementation of an Object Tracker on a Reconfigurable System on ChipFull-text access may be available. Sign in or learn about subscription options.pp. 230
Author Index
Author IndexFreely available from IEEE.pp. 237-238
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