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Integrated Circuit Design and System Design, Symposium on

Sept. 18 2000 to Sept. 24 2000

Manaus, Brazil

ISBN: 0-7695-0843-X

Table of Contents

Proceedings 13th Symposium on Integrated Circuits and Systems Design (Cat. No.PR00843)Freely available from IEEE.pp. i-i
ForewordFreely available from IEEE.pp. x
Conference OrganizersFreely available from IEEE.pp. xi
Program CommitteeFreely available from IEEE.pp. xii
ReviewersFreely available from IEEE.pp. xiii
Sponsoring SocietiesFreely available from IEEE.pp. xiv
Session 1-Design for Test
Some Experiments in Test Pattern Generation for FPGA-Implemented Combinational CircuitsFull-text access may be available. Sign in or learn about subscription options.pp. 3
by M. Renovell, J.M. Portal, P. Faure, J. Figueras, Y. Zorian
Session 1-Design for Test
Solving the I/O Bandwidth Problem in System on a Chip TestingFull-text access may be available. Sign in or learn about subscription options.pp. 9
by W. Maroufi, M. Benabdenbi, M. Marzouki
Session 1-Design for Test
Testability Properties of Vertex Precedent BDDsFull-text access may be available. Sign in or learn about subscription options.pp. 15
by A. Reis, A. Prado, M. Lubaszewski
Session 1-Design for Test
ATG-Based Timing Analysis of Circuits Containing Complex GatesFull-text access may be available. Sign in or learn about subscription options.pp. 21
by J.L. Guntzel, A.C. Medina Pinto, E. d'Avila, R. Reis
Session 2-Microarchitectures-Architecture
A Bit Scalable Architecture for Fuzzy Processors with Three Inputs and a Flexible Fuzzification UnitFull-text access may be available. Sign in or learn about subscription options.pp. 29
by R. d'Amore
Session 2-Microarchitectures-Architecture
Partitioned Branch Condition Resolution LogicFull-text access may be available. Sign in or learn about subscription options.pp. 35
by A. Farooqui, K.W. Current, V.G. Oklobdzija
Session 2-Microarchitectures-Architecture
Synthesis of High Performance Extended Burst Mode Asynchronous State MachinesFull-text access may be available. Sign in or learn about subscription options.pp. 41
by D. Lopes de Oliveira, M. Strum, Wang Jiang Chau, W. Chiepa Cunha
Session 2-Microarchitectures-Architecture
Improved IDEAFull-text access may be available. Sign in or learn about subscription options.pp. 47
by S.L.C. Salomao, J.M.S. de Alcantara, V.C. Alves, F.M.G. Franca
Session 3-Logic Design
Revisiting Hamiltonian Decomposition of the HypercubeFull-text access may be available. Sign in or learn about subscription options.pp. 55
by K. Okuda, S.W. Song
Session 3-Logic Design
An Input-Output Encoding Approach for Serial DecompositionFull-text access may be available. Sign in or learn about subscription options.pp. 61
by V. Muthukumar, R. Bignall, H. Selvaraj
Session 3-Logic Design
Disjunctive Decomposition of Switching Functions Using Symmetry InformationFull-text access may be available. Sign in or learn about subscription options.pp. 69
by M. Chrzanowska-Jeske, Wei Wang, Jing Xia, M. Jeske
Session 3-Logic Design
Methods Based on Petri Net for Resource Sharing EstimationFull-text access may be available. Sign in or learn about subscription options.pp. 75
by P. Maciel, F. Cruz Filho, E. Barros, W. Rosenstiel
Session 4-Analog Design
Robust Implementation and Statistical Modeling of a VI-ConverterFull-text access may be available. Sign in or learn about subscription options.pp. 83
by A. Graupner, R. Schuffny
Session 4-Analog Design
Resizing Rules for the Reuse of MOS Analog DesignsFull-text access may be available. Sign in or learn about subscription options.pp. 89
by C. Galup-Montoro, M.C. Schneider
Session 4-Analog Design
Analysis and Design of a Family of Low-Power Class AB Operational AmplifiersFull-text access may be available. Sign in or learn about subscription options.pp. 94
by F. Silveira, D. Flandre
Session 4-Analog Design
A Generator of Trapezoidal Association of Transistors (TAT): Improving Analog Circuits in a Pre-Diffused Transistor ArrayFull-text access may be available. Sign in or learn about subscription options.pp. 99
by A. Luiz Aita, S. Bampi, Jung Hyun Choi
Session 5-High Level Synthesis
Address Satisfaction for Storage Files with Fifos or Stacks during Scheduling of DSP AlgorithmsFull-text access may be available. Sign in or learn about subscription options.pp. 107
by C.A. Alba Pinto, K. van Eijk, B. Mesman, J. Jess
Session 5-High Level Synthesis
Register Binding for Predicated Execution in DSP ApplicationsFull-text access may be available. Sign in or learn about subscription options.pp. 113
by Q. Zhao, C.A.J. van Eijk, C.A. Alba Pinto, J.A.G. Jess
Session 5-High Level Synthesis
A Data Path Synthesis Method to Self-Testable Application Specific Integrated Circuit (ASIC)Full-text access may be available. Sign in or learn about subscription options.pp. 119
by J. Perez R. Cost, J. Vieira do Vale Neto
Session 5-High Level Synthesis
From a Hyperdocument-Centric to an Object-Oriented Approach for the Cave ProjectFull-text access may be available. Sign in or learn about subscription options.pp. 125
by L. Soares Indrusiak, R. Augusto da Luz Reis
Session 6-Physical Design
WTROPIC: A WWW-Based Macro-Cell GeneratorFull-text access may be available. Sign in or learn about subscription options.pp. 133
by J.L. Fragoso, F. Moraes, R. Reis
Session 6-Physical Design
Modular Exponentiation on Fine-Grained FPGAFull-text access may be available. Sign in or learn about subscription options.pp. 139
by A. Tiountchik, E. Trichina
Session 6-Physical Design
Net by Net Routing with a New Path Search AlgorithmFull-text access may be available. Sign in or learn about subscription options.pp. 144
by M. Johann, R. Reis
Session 6-Physical Design
Digital Circuit Design Based on the Resonant-Tunneling-Hetero-Junction-Bipolar-TransistorFull-text access may be available. Sign in or learn about subscription options.pp. 150
by P. Glosekotter, C. Pacha, K.F. Goser, G.I. Wirth, W. Prost, U. Auer, M. Agethen, P. Velling, F.J. Tegude
Session 7-System Level Design
On the Choice of Models of Computation for Writing Executable Specifications of System Level DesignsFull-text access may be available. Sign in or learn about subscription options.pp. 159
by I. Jeukens, M. Strum
Session 7-System Level Design
Functional Redundancy for Dynamic Exploitation of Performance-Energy Consumption Trade-OffsFull-text access may be available. Sign in or learn about subscription options.pp. 165
by V.M. Goulart Ferreira, H. Yasuura
Session 7-System Level Design
Modeling an E1/TU12 Mapper for SDH SystemsFull-text access may be available. Sign in or learn about subscription options.pp. 171
by R. Silveira, W.A.M. Van Noije
Testing mixed-signal coresFull-text access may be available. Sign in or learn about subscription options.pp. 307,308,309,310,311,312
by G. Huertas, D. Vazquez, E. Peralias, A. Rueda, J.L. Huertas
Session 7-System Level Design
JPEG Decoding in an Electronic Voting MachineFull-text access may be available. Sign in or learn about subscription options.pp. 177
by R. Pezzuol Jacobi, F. Trindade, J. Porfirio A. de Carvalh, R. Cantanhede
Session 8-Industrial Applications/Applications of FPGAs
An FPGA Implementation of the ATM LayerFull-text access may be available. Sign in or learn about subscription options.pp. 185
by J.A. Gomes de Lima, E.U.K. Melchier, H. Soares da Silva
Session 8-Industrial Applications/Applications of FPGAs
Prototyping a Pager-Like Device Using FPGAs: Design of an Object FinderFull-text access may be available. Sign in or learn about subscription options.pp. 191
by G.A. Cerezo Vasquez, W.A.M. Van Noije, S.E. Barbin
Session 8-Industrial Applications/Applications of FPGAs
Jet Determination in Liquid Argon Calorimeters Using a Heavily Interconnected System of Field Programmable Gate ArraysFull-text access may be available. Sign in or learn about subscription options.pp. 197
by B. Dulny, J. Fent, W. Haberer, C. Kiesling, A. Osthoff
Session 8-Industrial Applications/Applications of FPGAs
Prototyping of a Biologically-Plausible Vision System for Robotic ApplicationsFull-text access may be available. Sign in or learn about subscription options.pp. 202
by R. Zapata, P. Lepinay, L. Torres, J. Droulez, V. Creuze
Session 9-Digital Design
Hybrid latch Flip-Flop with Improved Power EfficiencyFull-text access may be available. Sign in or learn about subscription options.pp. 211
by N. Nedovic, V.G. Oklobdzija
Session 9-Digital Design
SisECO: Design of an Echo-Canceling IC for Base Band ModemsFull-text access may be available. Sign in or learn about subscription options.pp. 216
by L. Agostini, G. Stemmer, A. Prado, R. Pacheco, T. Campos, S. Bampi, R. Reis
Session 9-Digital Design
Modeling of Short Circuit Power Consumption Using Timing-Only Logic Cell MacromodelsFull-text access may be available. Sign in or learn about subscription options.pp. 222
by E.A.C. da Costa, F.P. Cortes, R. Cardoso, L. Carro, S. Bampi
Session 9-Digital Design
The Use of Extended TSPC CMOS Structures to Build Circuits with Doubled Input/Output Data ThroughputFull-text access may be available. Sign in or learn about subscription options.pp. 228
by J. Navarro, W.A.M. Van Noije
Session 10-Fault Tolerant Design
Evaluation of a Soft Error Tolerance Technique Based on Time and/or Space RedundancyFull-text access may be available. Sign in or learn about subscription options.pp. 237
by L. Anghel, D. Alexandrescu, M. Nicolaidis
Session 10-Fault Tolerant Design
Optimized Generation of VHDL Mutants for Injection of Transition ErrorsFull-text access may be available. Sign in or learn about subscription options.pp. 243
by R. Leveugle, K. Hadjiat
Session 10-Fault Tolerant Design
Recent Improvements on the Specification of Transient-Fault Tolerant VHDL Descriptions: A Case-Study for Area Overhead AnalysisFull-text access may be available. Sign in or learn about subscription options.pp. 249
by F. Vargas, A. Amory
Session 10-Fault Tolerant Design
Designing a Radiation Hardened 8051-Like Micro-ControllerFull-text access may be available. Sign in or learn about subscription options.pp. 255
by F.G. de Lima, E. Cota, L. Carro, M. Lubaszewski, R. Reis, R. Velazco, S. Rezgui
Session 11-Formal Methods and H/S Co-Design
JADE: An Embedded Systems Specification, Code Generation and Optimization ToolFull-text access may be available. Sign in or learn about subscription options.pp. 263
by C.L. Pereira, D.C. da Silva, Jr., R.G. Duarte, A.O. Fernandes, L.H. Canaan, C.J.N. Coelho, Jr., L.L. Ambrosio
Session 11-Formal Methods and H/S Co-Design
An ACL2 Model of VHDL for Symbolic Simulation and Formal VerificationFull-text access may be available. Sign in or learn about subscription options.pp. 269
by V. Moraes Rodrigues, D. Borrione, P. Georgelin
Session 11-Formal Methods and H/S Co-Design
A New Approach to Solving the Hardware-Software Partitioning Problem in Embedded System DesignFull-text access may be available. Sign in or learn about subscription options.pp. 275
by D.W. Engels, S. Devadas
Session 11-Formal Methods and H/S Co-Design
Design of a Classification System for Rectangular Shapes Using a Co-Design EnvironmentFull-text access may be available. Sign in or learn about subscription options.pp. 281
by R.F. Molz, P.M. Engel, F.G. Moraes, L. Torres, M. Robert
Session 12-Analog and Mixed-Signal Design
Fault Models and Compact Test Vectors for MOS OpAmp circuitsFull-text access may be available. Sign in or learn about subscription options.pp. 289
by J.V. Calvano, V.C. Alves, M.S. Lubaszewski, A.C. Mesquita
Session 12-Analog and Mixed-Signal Design
Toward Analog Circuit Synthesis: A Global Methodology Based upon Design of ExperimentsFull-text access may be available. Sign in or learn about subscription options.pp. 295
by Y. Deval, J.-B. Begueret, J. Tomas, P. Fouillat
Session 12-Analog and Mixed-Signal Design
A JAVA-Based Mixed-Signal Design EnvironmentFull-text access may be available. Sign in or learn about subscription options.pp. 301
by J. Mades, T. Schneider, M. Glesner, A. Windisch, W. Ecker
Session 12-Analog and Mixed-Signal Design
Testing Mixed-Signal CoresFull-text access may be available. Sign in or learn about subscription options.pp. 307
Session 13-Physical Modeling
What is the Appropriate Model for Crosstalk Control?Full-text access may be available. Sign in or learn about subscription options.pp. 315
by L. Scheffer
Session 13-Physical Modeling
Efficient /spl nu/MOS Realization of Threshold Voters for Self-Purging RedundancyFull-text access may be available. Sign in or learn about subscription options.pp. 321
by J.M. Quintana, M.J. Avedillo, E. Rodriguez-Villegas, A. Rueda
Session 13-Physical Modeling
LASCA-Interconnect Parasitic Extraction Tool for Deep-Submicron IC DesignFull-text access may be available. Sign in or learn about subscription options.pp. 327
by F.K. Ferreira, F. Moraes, R. Reis
Session 13-Physical Modeling
An Integrated Circuit for the in Situ Characterization of CMOS Best-Process MicromachiningFull-text access may be available. Sign in or learn about subscription options.pp. 333
by B. Warneke, K.S.J. Pister
Session 14-Reconfigurable Hardware
An Application-Tailored Dynamically Reconfigurable Hardware Architecture for Digital Baseband ProcessingFull-text access may be available. Sign in or learn about subscription options.pp. 341
by J. Becker, T. Pionteck, M. Glesner
Session 14-Reconfigurable Hardware
Exploiting FPGA-Based Architectures and Design Tools for Problems of Reconfigurable ComputationsFull-text access may be available. Sign in or learn about subscription options.pp. 347
by I. Skliarova, A.B. Ferrari
Session 14-Reconfigurable Hardware
Synthesis of Control Circuits with Dynamically Modifiable Behavior on the Basis of Statically Reconfigurable FPGAsFull-text access may be available. Sign in or learn about subscription options.pp. 353
by V. Sklyarov
Session 14-Reconfigurable Hardware
Implementation of Cryptographic Applications on the Reconfigurable FPGA Coprocessor microEnableFull-text access may be available. Sign in or learn about subscription options.pp. 359
by H. Singpiel, H. Simmler, A. Kugel, R. Manner, A.C.C. Vieira, F. Galvez-Durand, J.M.S. de Alcantara, V.C. Alves
Session 15-Low-Power, Low-Voltage
Limits to Voltage Scaling from the Low Power PerspectiveFull-text access may be available. Sign in or learn about subscription options.pp. 365
by A. Forestier, M.R. Stan
Session 15-Low-Power, Low-Voltage
Adaptive Partial Businvert Encoding for Power Efficient Data Transfer over Wide System BusesFull-text access may be available. Sign in or learn about subscription options.pp. 371
by R. Siegmund, C. Kretzschmar, D. Muller
Session 15-Low-Power, Low-Voltage
Energy-Efficient Register AccessFull-text access may be available. Sign in or learn about subscription options.pp. 377
by J.H. Tseng, K. Asanovic
Session 16-Embedded Systems
Design and Simulation of Heterogeneous Embedded SystemsFull-text access may be available. Sign in or learn about subscription options.pp. 385
by K.D. Mueller-Glaser, E. Sax, W. Stork, A. Wagner, J. Drescher, M. Kuehl
Session 16-Embedded Systems
A Comparison of OO and Reactive Based Specifications on the Design of Embedded SystemsFull-text access may be available. Sign in or learn about subscription options.pp. 391
by S.A. Ito, J.C.B. de Mattos, L. Carro, S.S. Toscani
Session 16-Embedded Systems
A Comparison of Microcontrollers Targeted to FPGA-Based Embedded ApplicationsFull-text access may be available. Sign in or learn about subscription options.pp. 397
by S.A. Ito, L. Carro
Session 16-Embedded Systems
Author IndexFreely available from IEEE.pp. 403
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