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Proceedings 15th Symposium on Integrated Circuits and Systems Design

Sept. 14 2002 to Sept. 14 2002

Porto Alegre, Brazil

Table of Contents

Introduction
ForewardFreely available from IEEE.pp. x
Introduction
Conference OrganizersFreely available from IEEE.pp. xi
Introduction
Program CommitteeFreely available from IEEE.pp. xii
Introduction
ReviewersFreely available from IEEE.pp. xiii
Introduction
Sponsoring SocietiesFull-text access may be available. Sign in or learn about subscription options.pp. xiv
Session 1 — Digital Design 1
Two Hardware Implementations for the Montgomery Modular Multiplication: Sequential versus ParallelFull-text access may be available. Sign in or learn about subscription options.pp. 3
Session 1 — Digital Design 1
Analysis and Implementation of a Stochastic Multiplier for Electrical Power MeasurementFull-text access may be available. Sign in or learn about subscription options.pp. 9
Session 1 — Digital Design 1
A New Architecture for 2?s Complement Gray Encoded Array MultiplierFull-text access may be available. Sign in or learn about subscription options.pp. 14
Session 1 — Digital Design 1
Architectural Synthesis of Finite Impulse Response Digital FiltersFull-text access may be available. Sign in or learn about subscription options.pp. 20
Session 2a — Digital Design - ATM
HW/SW Codesign of Handoff Protocol for Wireless ATM Networks Based on Performance Optimization Using Genetic AlgorithmFull-text access may be available. Sign in or learn about subscription options.pp. 29
Session 2a — Digital Design - ATM
APU: Specification and Design of a Multi Algorithm ATM Policing Unit IPFull-text access may be available. Sign in or learn about subscription options.pp. 35
Session 2b — Computer Architecture
Multithreaded Architectural Support for Speculative Trace Scheduling in VLIW ProcessorsFull-text access may be available. Sign in or learn about subscription options.pp. 43
Session 2b — Computer Architecture
A Novel Method for Improving the Operation Autonomy of SIMD Processing ElementsFull-text access may be available. Sign in or learn about subscription options.pp. 49
Session 3a — Analog Design 1
An Integrated CMOS Instrumentation Amplifier with Improved CMRRFull-text access may be available. Sign in or learn about subscription options.pp. 57
Session 3a — Analog Design 1
A Continuous-Time Incremental Analog to Digital ConverterFull-text access may be available. Sign in or learn about subscription options.pp. 62
Session 3a — Analog Design 1
Capacitor Charge Control Technique Applied to Digitally Programmable IIR Switched-Capacitor FilterFull-text access may be available. Sign in or learn about subscription options.pp. 68
Session 3a — Analog Design 1
Analog Decimator IC in Direct-form Polyphase StructureFull-text access may be available. Sign in or learn about subscription options.pp. 74
Session 3b — Test and Fault Tolerance
Testability Properties of BDDsFull-text access may be available. Sign in or learn about subscription options.pp. 83
Reducing test application time through interleaved scanFull-text access may be available. Sign in or learn about subscription options.pp. 89-94
Session 3b — Test and Fault Tolerance
Analyzing Area and Performance Penalty of Protecting Different Digital Modules with Hamming Code and Triple Modular RedundancyFull-text access may be available. Sign in or learn about subscription options.pp. 95
A software fault tolerance method for safety-critical systems: effectiveness and drawbacksFull-text access may be available. Sign in or learn about subscription options.pp. 101-106
Session 4 — Codesign 1
Interface Generation for Concurrent Processes During Hardware/Software Co-synthesisFull-text access may be available. Sign in or learn about subscription options.pp. 109
Session 4 — Codesign 1
A Heterogeneous and Distributed Co-Simulation EnvironmentFull-text access may be available. Sign in or learn about subscription options.pp. 115
Session 4 — Codesign 1
A Study on Communication Issues for Systems-on-ChipFull-text access may be available. Sign in or learn about subscription options.pp. 121
Session 4 — Codesign 1
A Study on a Garbage Collector for Embedded ApplicationsFull-text access may be available. Sign in or learn about subscription options.pp. 127
Session 5a — Analog Testing
A Noise Generator for Analog-to-Digital Converter TestingFull-text access may be available. Sign in or learn about subscription options.pp. 135
Session 5a — Analog Testing
A Statistical Sampler for Increasing Analog Circuits ObservabilityFull-text access may be available. Sign in or learn about subscription options.pp. 141
Session 5b — Low Power 1
A Methodology for Dynamic Power Consumption Estimation Using VHDL DescriptionsFull-text access may be available. Sign in or learn about subscription options.pp. 149
Session 5b — Low Power 1
Power Consumption in Point-to-Point Interconnect ArchitecturesFull-text access may be available. Sign in or learn about subscription options.pp. 155
Session 6a — Design Methodology
Collaborative Design Using a Shared Object Spaces InfrastructureFull-text access may be available. Sign in or learn about subscription options.pp. 163
Session 6a — Design Methodology
Experiences on Analog Circuit Technology Migration and ReuseFull-text access may be available. Sign in or learn about subscription options.pp. 169
Session 6b — Reconfigurable Architecture
Techniques and Mechanisms for Dynamic Reconfiguration in an Image ProcessorFull-text access may be available. Sign in or learn about subscription options.pp. 177
Session 6b — Reconfigurable Architecture
Core Communication Interface for FPGAsFull-text access may be available. Sign in or learn about subscription options.pp. 183
Session 7 — Digital Design 2
A Low-Cost FPGA Implementation of the Advanced Encryption Standard AlgorithmFull-text access may be available. Sign in or learn about subscription options.pp. 191
Session 7 — Digital Design 2
An IP of an Advanced Encryption Standard for Altera™ DevicesFull-text access may be available. Sign in or learn about subscription options.pp. 197
Session 7 — Digital Design 2
Pipelined Entropy Coders for JPEG CompressionFull-text access may be available. Sign in or learn about subscription options.pp. 203
Session 7 — Digital Design 2
Signal Processing Applications for Embedded Java SystemsFull-text access may be available. Sign in or learn about subscription options.pp. 209
Session 8a — Low Power 2
Power Management Exploration for a Block Turbo DecoderFull-text access may be available. Sign in or learn about subscription options.pp. 217
Session 8a — Low Power 2
Low-Power Control Architecture for Embedded ProcessorsFull-text access may be available. Sign in or learn about subscription options.pp. 221
Session 8b — Codesign 2
Exception Handling with Petri Net for Digital SystemsFull-text access may be available. Sign in or learn about subscription options.pp. 229
Session 8b — Codesign 2
CDFG -Petri Net Temporal Partitioning for Switching Context ApplicationsFull-text access may be available. Sign in or learn about subscription options.pp. 235
Session 9a — Analog Design 2
An Offset Self-Correction Sample and Hold Circuit for Precise Applications in Low Voltage CMOSFull-text access may be available. Sign in or learn about subscription options.pp. 243
Session 9a — Analog Design 2
Operational Amplifier Power Optimization for a Given Total (Slewing plus Linear) Settling TimeFull-text access may be available. Sign in or learn about subscription options.pp. 247
Session 9a — Analog Design 2
A Switched-MOSFET Programmable Low-Voltage FilterFull-text access may be available. Sign in or learn about subscription options.pp. 254
Session 9a — Analog Design 2
Low-Voltage ADC for Sample to Serial Interface ApplicationsFull-text access may be available. Sign in or learn about subscription options.pp. 258
Session 9b — Physical Design
Automatic Generation of Digital Cell LibrariesFull-text access may be available. Sign in or learn about subscription options.pp. 265
Session 9b — Physical Design
A LEGAL Algorithm Following Global RoutingFull-text access may be available. Sign in or learn about subscription options.pp. 271
Session 9b — Physical Design
Finding the Critical Delay of Combinational Blocks by Floating Vector Simulation and Path TracingFull-text access may be available. Sign in or learn about subscription options.pp. 277
Session 9b — Physical Design
Compression and Technology Mapping of Logic CircuitsFull-text access may be available. Sign in or learn about subscription options.pp. 283
Session 10 — Analog Modeling
CMOS OTA Sizing Using ACM Model in a Graphical ApproachFull-text access may be available. Sign in or learn about subscription options.pp. 289
Session 10 — Analog Modeling
Design of Active Inductors Using CMOS TechnologyFull-text access may be available. Sign in or learn about subscription options.pp. 296
Session 10 — Analog Modeling
On Generating Compact, Passive Models of Frequency-Described SystemsFull-text access may be available. Sign in or learn about subscription options.pp. 302
Session 10 — Analog Modeling
Behavioral Modeling of Analogue and Mixed Integrated Systems with VHDL-AMS for RF ApplicationsFull-text access may be available. Sign in or learn about subscription options.pp. 308
Session 11a — Codesign 3
On the Importance, Problems and Solutions of Pointer SynthesisFull-text access may be available. Sign in or learn about subscription options.pp. 317
Session 11a — Codesign 3
Requirements, Primitives and Models for Systems SpecificationFull-text access may be available. Sign in or learn about subscription options.pp. 323
Session 11b — Digital Design 3
System on a Chip for Petroleum Pipeline InspectionFull-text access may be available. Sign in or learn about subscription options.pp. 331
Session 11b — Digital Design 3
Combined Turbo and Convolutional Decoder Architecture for UMTS Wireless ApplicationsFull-text access may be available. Sign in or learn about subscription options.pp. 337
Session 12a — Analog Design 3
CMOS Bandgap with Base-Current Thermal CompensationFull-text access may be available. Sign in or learn about subscription options.pp. 345
Session 12a — Analog Design 3
A 4 Gsamples/S with 2-4 GHz Input Bandwidth SIGE Digitizer for Radio Astronomy ApplicationsFull-text access may be available. Sign in or learn about subscription options.pp. 350
Session 12b — Digital Design 4
Minimizing the Number of Paths in BDDsFull-text access may be available. Sign in or learn about subscription options.pp. 359
Embedded Tutorials
Configurable Systems-on-Chip (CSoC)Full-text access may be available. Sign in or learn about subscription options.pp. 379
Embedded Tutorials
A Structural Test Methodology for SRAM-Based FPGAsFull-text access may be available. Sign in or learn about subscription options.pp. 385
Embedded Tutorials
Ultra Low-Energy Transceivers for Wireless Sensor NetworksFull-text access may be available. Sign in or learn about subscription options.pp. 386
Embedded Tutorials
Parametric Yield Estimation for Deep Sub- Micron VLSI CircuitsFull-text access may be available. Sign in or learn about subscription options.pp. 387
Author Index
Author IndexFreely available from IEEE.pp. 389
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