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Proceedings
SLIP
SLIP 2015
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2015 ACM/IEEE International Workshop on System Level Interconnect Prediction (SLIP)
June 6 2015 to June 6 2015
San Francisco, CA, USA
Table of Contents
2015 ACM/IEEE International Workshop on System Level Interconnect Prediction (SLIP) [Cover]
Freely available from IEEE.
pp. c1
Copyright
Freely available from IEEE.
pp. 1-1
SI for free: machine learning of interconnect coupling delay and transition effects
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pp. 1-8
by
Andrew B. Kahng
,
Mulong Luo
,
Siddhartha Nath
Smart I/Os: a data-pattern aware 2.5D interconnect with space-time multiplexing
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pp. 1-6
by
Sai Manoj
,
Kanwen Wang
,
Hantao Huang
,
Hao Yu
Compact modeling and system implications of microring modulators in nanophotonic interconnects
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pp. 1-6
by
Rui Wu
,
Chin-Hui Chen
,
Jean-Marc Fedeli
,
Maryse Fournier
,
Raymond G. Beausoleil
,
Kwang-Ting Cheng
Clock clustering and IO optimization for 3D integration
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pp. 1-8
by
Samyoung Bang
,
Kwangsoo Han
,
Andrew B. Kahng
,
Vaishnav Srinivas
On fast timing closure: speeding up incremental path-based timing analysis with mapreduce
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pp. 1-6
by
,
Power line communication for hybrid power/signal pin SOC design
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pp. 1-8
by
Xiang Zhang
,
Yang Liu
,
Ryan Coutts
,
Lynx: a self-organizing wireless sensor network with commodity palmtop computers
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pp. 1-7
by
Haifeng Xu
,
Melissa M. Bilec
,
William O. Collinge
,
Laura A. Schaefer
,
Amy E. Landis
,
Alex K. Jones
Multi-product floorplan and uncore design framework for chip multiprocessors
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pp. 1-7
by
Marco Escalante
,
Andrew B. Kahng
,
Michael Kishinevsky
,
Umit Ogras
,
Kambiz Samadi
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