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Proceedings
SLIP
SLIP 2016
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2016 ACM/IEEE International Workshop on System Level Interconnect Prediction (SLIP)
June 4 2016 to June 4 2016
Austin, TX, USA
Table of Contents
A comparative analysis of front-end and back-end compatible silicon photonic on-chip interconnects
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pp. 1-8
by
Ishan G. Thakkar
,
Sai Vineel Reddy Chittamuru
,
Sudeep Pasricha
Latch clustering for minimizing detection-to-boosting latency toward low-power resilient circuits
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pp. 1-6
by
Chih-cheng Hsu
,
Mark Po-hung Lin
,
Masanori Hashimoto
Connectivity effects on energy and area for neuromorphic system with high speed asynchronous pulse mode links
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pp. 1-7
by
Carrie Segal
,
Aditya Dalakoti
,
Merritt Miller
,
Forrest Brewer
Buffered interconnects in 3D IC layout design
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pp. 1-8
by
Mohammad A. Ahmed
,
Sucheta Mohapatra
,
Malgorzata Chrzanowska-Jeske
Topologically-geometric routing
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pp. 1-6
by
Roman Bazylevych
,
Marek Pałasinski
,
Lubov Bazylevych
Revisiting 3DIC Benefit with Multiple Tiers
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pp. 1-8
by
Wei-ting Jonas Chan
,
Andrew B. Kahng
,
Jiajia Li
Spin-hall assisted STT-RAM design and discussion
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pp. 1-4
by
Enes Eken
,
Ismail Bayram
,
Yaojun Zhang
,
Bonan Yan
,
Wenqing Wu
,
Hai Li
,
Yiran Chen
A demand-aware predictive dynamic bandwidth allocation mechanism for wireless network-on-chip
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pp. 1-8
by
Naseef Mansoor
,
Shahriar Shamim
,
Amlan Ganguly
[Front Matter]
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pp. 1-2
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