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2017 ACM/IEEE International Workshop on System Level Interconnect Prediction (SLIP)

June 17 2017 to June 17 2017

Austin, TX, USA

Table of Contents

[Copyright notice]Freely available from IEEE.pp. 1-1
Fence-aware detailed-routability driven placementFull-text access may be available. Sign in or learn about subscription options.pp. 1-7
by Wing-Kai Chow, Jian Kuang, Peishan Tu, Evangeline F.Y. Young
Analyzing voltage bias and temperature induced aging effects in photonic interconnects for manycore computingFull-text access may be available. Sign in or learn about subscription options.pp. 1-8
by Sai Vineel Reddy Chittamuru, Ishan G. Thakkar, Sudeep Pasricha
Reconfigurable topology synthesis for application-specific noc on partially dynamically reconfigurable FPGAsFull-text access may be available. Sign in or learn about subscription options.pp. 1-8
by Jinglei Huang, Xiaodong Xu, Lan Yao, Song Chen
Timing driven routing tree constructionFull-text access may be available. Sign in or learn about subscription options.pp. 1-8
by Peishan Tu, Wing-Kai Chow, Evangeline F.Y. Young
A charge recovery logic system busFull-text access may be available. Sign in or learn about subscription options.pp. 1-4
by Leo Filippini, Baris Taskin
Slew-down: analysis of slew relaxation for low-impact clock buffersFull-text access may be available. Sign in or learn about subscription options.pp. 1-4
by Scott Lerner, Eric Leggett, Baris Taskin
Clock tree synthesis for heterogeneous 3-D integrated circuitsFull-text access may be available. Sign in or learn about subscription options.pp. 1-6
by Isuru Daulagala, Ioannis Savidis
Frontiers of timingFull-text access may be available. Sign in or learn about subscription options.pp. 1-4
by Ulf Schlichtmann
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