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Memory Technology, Design and Testin, IEEE International Workshop on

Aug. 6 2001 to Aug. 7 2001

San Jose, California

ISBN: 0-7695-1242-9

Table of Contents

2001 IEEE International Workshop on Memory Technology, Design and Testing [front matter]Freely available from IEEE.pp. ii-v
Message from the ChairsFreely available from IEEE.pp. vii
Conference CommitteeFreely available from IEEE.pp. viii
TTTC InformationFull-text access may be available. Sign in or learn about subscription options.pp. 106
Session 1: Memory Design
A DRAM Compiler for Fully Optimized Memory InstancesFull-text access may be available. Sign in or learn about subscription options.pp. 0003
by G. Harling
Session 1: Memory Design
Orthogonal Transpose-RAM Cell Array Architecture with Alternate Bit-Line To Bit-Line Contact SchemeFull-text access may be available. Sign in or learn about subscription options.pp. 0009
by Kyung-Saeng Kim, KwangMyoung Rho, Kwyro Lee
Session 1: Memory Design
Design of an Embedded Fully-Depleted SOI SRAMFull-text access may be available. Sign in or learn about subscription options.pp. 0013
by Raymond J. Sung, John C. Koob, Tyler L. Brandon, Duncan G. Elliott, Bruce F. Cockburn
Session 2: Memory BIST
A P1500 Compliant Programable BistShell for Embedded MemoriesFull-text access may be available. Sign in or learn about subscription options.pp. 0021
by Sandeep Koranne, Tom Waayers, Robert Beurze, Clemens Wouters, Sunil Kumar, G. S. Visweswaran
Session 2: Memory BIST
BIST-Based Bitfail Mapping of an Embedded DRAMFull-text access may be available. Sign in or learn about subscription options.pp. 0029
by Brian R. Kessler, Jeffrey Dreibelbis, Tim McMahon, Joshua S. McCloy, Rex Kho
Session 5: Redundancy and Error Control
A Method to Caculate Redundancy Coverage for FLASH MemoryFull-text access may be available. Sign in or learn about subscription options.pp. 0041
by S. Matarrese, L. Fasoli
Session 5: Redundancy and Error Control
An Error Control Code Scheme for Multilevel Flash MemoriesFull-text access may be available. Sign in or learn about subscription options.pp. 0045
by Stefano Gregori, Guido Torelli, Osama Khouri, Rino Micheloni
Session 5: Redundancy and Error Control
An Approach for Evaluation of Redunancy Analysis AlgorithmsFull-text access may be available. Sign in or learn about subscription options.pp. 0051
by S. Shoukourian, V. Vardanian, Y. Zorian
Session 6: Fault Models and Multi-Port SRAM Testing
Transient Faults in DRAMs: Concepts, Analysis and Impact on TestsFull-text access may be available. Sign in or learn about subscription options.pp. 0059
by Zaid Al-Ars, Ad J. van de Goor
Session 6: Fault Models and Multi-Port SRAM Testing
Realistic Fault Models and Test Procedures for Multi-Port SRAMsFull-text access may be available. Sign in or learn about subscription options.pp. 0065
by Said Hamdioui, Ad J. van de Goor, David Eastwick, Mike Rodgers
Session 6: Fault Models and Multi-Port SRAM Testing
A Parallel Approach for Testing Multi-Port Static Random Access MemoriesFull-text access may be available. Sign in or learn about subscription options.pp. 0073
by F. Karimi, F. Lombardi, S. Irrinki, T. Crosby
Session 7: Verification and Test
Equivalence Checking a 256MB SDRAMFull-text access may be available. Sign in or learn about subscription options.pp. 0085
by Simon Napper, Dian Yang
Session 7: Verification and Test
Testing Carry Logic Modules of SRAM-based FPGAsFull-text access may be available. Sign in or learn about subscription options.pp. 0091
by Xiaoling Sun, Jian Xu, Pieter Trouborst
Session 7: Verification and Test
Low Output Resistance Charge Pump for Flash Memory ProgrammingFull-text access may be available. Sign in or learn about subscription options.pp. 0099
by Osama Khouri, Stefano Gregori, Dario Soltesz, Guido Torelli, Rino Micheloni
Session 7: Verification and Test
Author IndexFreely available from IEEE.pp. 0105
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