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Proceedings of International Test Conference

Oct. 2 1995 to Oct. 6 1994

Washington, DC, USA

Table of Contents

Proceedings International Test Conference 1994Full-text access may be available. Sign in or learn about subscription options.pp. ii-xi
Development of a solution for achieving known-good-dieFull-text access may be available. Sign in or learn about subscription options.pp. 15-21
by L. Prokopchak
Membrane probe technology for MCM Known-Good-DieFull-text access may be available. Sign in or learn about subscription options.pp. 22,23,24,25,26,27,28,29
by T. Ueno, Y. Kondoh
High yield multichip modules based on minimal IC pretestFull-text access may be available. Sign in or learn about subscription options.pp. 30,31,32,33,34,35,36,37,38,39,40
by W. Burdick, W. Daum
Feasibility study of smart substrate multichip modulesFull-text access may be available. Sign in or learn about subscription options.pp. 41,42,43,44,45,46,47,48,49
by A.E. Gattiker, W. Maly
Testability strategy of the Alpha AXP 21164 microprocessorFull-text access may be available. Sign in or learn about subscription options.pp. 50,51,52,53,54,55,56,57,58,59
by D.K. Bhavsar, J.H. Edmondson
Testability features of the MC68060 microprocessorFull-text access may be available. Sign in or learn about subscription options.pp. 60,61,62,63,64,65,66,67,68,69
by A.L. Crouch, M. Pressly, J. Circello
MicroSPARC: a case-study of scan based debugFull-text access may be available. Sign in or learn about subscription options.pp. 70,71,72,73,74,75
by K. Holdbrook, S. Joshi, S. Mitra, J. Petolino, R. Raman, M. Wong
Balancing structured and ad-hoc design for test: testing of the PowerPC 603 microprocessorFull-text access may be available. Sign in or learn about subscription options.pp. 76,77,78,79,80,81,82,83
by C. Hunter, E.K. Vida-Torku, J. LeBlanc
System test cost modelling based on event rate analysisFull-text access may be available. Sign in or learn about subscription options.pp. 84,85,86,87,88,89,90,91,92
by D. Farren, A.P. Ambler
ASIC test cost/strategy trade-offsFull-text access may be available. Sign in or learn about subscription options.pp. 93,94,95,96,97,98,99,100,101,102
by D.L. Wheater, P. Nigh, J.T. Mechler, L. Lacroix
A test process optimization and cost modeling toolFull-text access may be available. Sign in or learn about subscription options.pp. 103,104,105,106,107,108,109,110
by T.J. Moore
When does it make C to give up physical test access?Full-text access may be available. Sign in or learn about subscription options.pp. 111,112,113,114,115,116,117,118,119
by D.A. Greene
3B21D BIST/Boundary-Scan system diagnostic test storyFull-text access may be available. Sign in or learn about subscription options.pp. 120,121,122,123,124,125,126
by E.C. Behnke
Modeling for structured system interconnect testFull-text access may be available. Sign in or learn about subscription options.pp. 127,128,129,130,131,132,133
by F.W. Angelotti
System-level testability of hardware/software systemsFull-text access may be available. Sign in or learn about subscription options.pp. 134,135,136,137,138,139,140,141,142
by H.P.E. Vranken, M.P.J. Stevens, M.T.M. Segers, J.H.M.M. van Rhee
Fastpath: a path-delay test generator for standard scan designsFull-text access may be available. Sign in or learn about subscription options.pp. 154-163
by B. Underwood, Wai-On Law, S. Kang, H. Konuk
On path delay testing in a standard scan environmentFull-text access may be available. Sign in or learn about subscription options.pp. 164,165,166,167,168,169,170,171,172,173
by P. Varma
Automated logic synthesis of random pattern testable circuitsFull-text access may be available. Sign in or learn about subscription options.pp. 174,175,176,177,178,179,180,181,182,183
by N.A. Touba, E.J. McCluskey
Transforming behavioral specifications to facilitate synthesis of testable designsFull-text access may be available. Sign in or learn about subscription options.pp. 184,185,186,187,188,189,190,191,192,193
by S. Dey, M. Potkonjak
QTAG: a standard for test fixture based I/sub DDQ//I/sub SSQ/ monitorsFull-text access may be available. Sign in or learn about subscription options.pp. 194,195,196,197,198,199,200,201,202
by K. Baker
An off-chip IDDq current measurement unit for telecommunication ASICsFull-text access may be available. Sign in or learn about subscription options.pp. 203,204,205,206,207,208,209,210,211,212
by H.A.R. Manhaeve, P.L. Wrighton, J. van Sas, U. Swerts
Development of a class 1 QTAG monitorFull-text access may be available. Sign in or learn about subscription options.pp. 213,214,215,216,217,218,219,220,221,222
by K. Baker, A. Bratt, A. Richardson, A. Welbers
A serially addressable, flexible current monitor for test fixture based I/sub DDQ//I/sub SSQ/ testingFull-text access may be available. Sign in or learn about subscription options.pp. 223,224,225,226,227,228,229,230,231,232
by A. Hales
On the initialization of sequential circuitsFull-text access may be available. Sign in or learn about subscription options.pp. 233,234,235,236,237,238,239
by J.A. Wahbeh, D.G. Saab
An automatic test pattern generator for large sequential circuits based on Genetic AlgorithmsFull-text access may be available. Sign in or learn about subscription options.pp. 240-249
by P. Prinetto, M. Rebaudengo, M. Sonza Reorda
ATPG for heat dissipation minimization during test applicationFull-text access may be available. Sign in or learn about subscription options.pp. 250,251,252,253,254,255,256,257,258
by Seongmoon Wang, S.K. Gupta
Sequentially untestable faults identified without search ("simple implications beat exhaustive search!")Full-text access may be available. Sign in or learn about subscription options.pp. 259,260,261,262,263,264,265,266
by M.A. Iyer, M. Abramovici
Implementation of a dual segment architecture for a high pin count VLSI test systemFull-text access may be available. Sign in or learn about subscription options.pp. 267,268,269,270,271,272
by M.G. Davis
500 MHz testing on a 100 MHz testerFull-text access may be available. Sign in or learn about subscription options.pp. 273,274,275,276,277,278
by D. Wimmers, K. Sakaitani, B. West
Modeling the effect of ground bounce on noise marginFull-text access may be available. Sign in or learn about subscription options.pp. 279,280,281,282,283,284,285
by M.S. Haydt, R. Owens, S. Mourad
Modular mixed signal testing: high speed or high resolutionFull-text access may be available. Sign in or learn about subscription options.pp. 286,287,288,289,290
by E. Kushnick
Built-in system test and fault locationFull-text access may be available. Sign in or learn about subscription options.pp. 291,292,293,294,295,296,297,298,299
by G.R. McLeod
Roadmap for extending IEEE 1149.1 for hierarchical control of locally-stored, standardized command set, test programsFull-text access may be available. Sign in or learn about subscription options.pp. 300,301,302,303,304,305,306
by J. Andrews
Environmental Stress Testing with Boundary-ScanFull-text access may be available. Sign in or learn about subscription options.pp. 307,308,309,310,311,312,313
by D. Le, I. Karolik, R. Smith, A.J. Mcgovern, C. Curette, J. Ulbin, M. Zarubaiko, C. Henry, L. Stevens
An approach to accelerate scan testing in IEEE 1149.1 architecturesFull-text access may be available. Sign in or learn about subscription options.pp. 314,315,316,317,318,319,320,321,322
by L. Whetsel
Multi-frequency, multi-phase scan chainFull-text access may be available. Sign in or learn about subscription options.pp. 323,324,325,326,327,328,329,330
by Kee Sup Kim, L. Schultz
A test clock reduction method for scan-designed circuitsFull-text access may be available. Sign in or learn about subscription options.pp. 331,332,333,334,335,336,337,338,339
by Jau-Shien Chang, Chen-Shang Lin
Hybrid design for testability combining scan and clock line control and method for test generationFull-text access may be available. Sign in or learn about subscription options.pp. 340,341,342,343,344,345,346,347,348,349
by Sanghyeon Baeg, W.A. Rogers
In-system timing extraction and control through scan-based, test-access portsFull-text access may be available. Sign in or learn about subscription options.pp. 350,351,352,353,354,355,356,357,358,359
by A. DeHon
Testing 256k word/spl times/16 bit Cache DRAM (CDRAM)Full-text access may be available. Sign in or learn about subscription options.pp. 360
by Y. Konishi, T. Ogawa, M. Kumanoya
Testing high speed DRAMsFull-text access may be available. Sign in or learn about subscription options.pp. 361
by J.A. Gasbarro
Practical test methods for verification of the EDRAMFull-text access may be available. Sign in or learn about subscription options.pp. 362
by K. Stalnaker
Testing issues on high speed synchronous DRAMsFull-text access may be available. Sign in or learn about subscription options.pp. 363
by Wha-Joon Lee
BenchmarkingFull-text access may be available. Sign in or learn about subscription options.pp. 364
by K. Ruparel
Potential solutions for benchmarking issuesFull-text access may be available. Sign in or learn about subscription options.pp. 365
by D. Sterba
Multichip module testing methodologies: what's in; what's notFull-text access may be available. Sign in or learn about subscription options.pp. 366
by K. Posse
MCM test trade-offsFull-text access may be available. Sign in or learn about subscription options.pp. 367
by J. Eastman
Aliasing-free signature analysis for RAM BISTFull-text access may be available. Sign in or learn about subscription options.pp. 368,369,370,371,372,373,374,375,376,377
by V.N. Yarmolik, M. Nicolaidis, O. Kebichi
An effective BIST scheme for ring-address type FIFOsFull-text access may be available. Sign in or learn about subscription options.pp. 378,379,380,381,382,383,384,385,386,387
by Y. Zorian, A.J. Van de Goor, I. Schanstra
The PowerPC 603 microprocessor: an array built-in self test mechanismFull-text access may be available. Sign in or learn about subscription options.pp. 388,389,390,391,392,393,394
by C. Hunter, J. Slaton, J. Eno, R. Jessani, C. Dietz
Testing CMOS logic gates for: realistic shortsFull-text access may be available. Sign in or learn about subscription options.pp. 395,396,397,398,399,400,401,402
by B. Chess, A. Freitas, F.J. Ferguson, T. Larrabee
A study of I/sub DDQ/ subset selection algorithms for bridging faultsFull-text access may be available. Sign in or learn about subscription options.pp. 403,404,405,406,407,408,409,410,411,412
by S. Chakravarty, P. Thadikaran
Defect classes-an overdue paradigm for CMOS IC testingFull-text access may be available. Sign in or learn about subscription options.pp. 413,414,415,416,417,418,419,420,421,422,423,424,425
by C.F. Hawkins, J.M. Soden, A.W. Righter, F.J. Ferguson
A test methodology to support an ASEM MCM foundryFull-text access may be available. Sign in or learn about subscription options.pp. 426,427,428,429,430,431,432,433,434,435
by T. Storey, C. Lapihuska, E. Atwood, L. Su
Test strategies for a family of complex MCMsFull-text access may be available. Sign in or learn about subscription options.pp. 436,437,438,439,440,441,442,443,444,445
by A. Flint
Designing "dual personality" IEEE 1149.1 compliant multi-chip modulesFull-text access may be available. Sign in or learn about subscription options.pp. 446,447,448,449,450,451,452,453,454,455
by N. Jarwala
A case-study in the use of scan in microSPARC testing and debugFull-text access may be available. Sign in or learn about subscription options.pp. 456,457,458,459,460
by J. Katz
A hierarchical environment for interactive test engineeringFull-text access may be available. Sign in or learn about subscription options.pp. 461,462,463,464,465,466,467,468,469,470
by T. Burch, J. Hartmann, G. Hotz, M. Krallmann, U. Nikolaus, S.M. Reddy, U. Sparmann
Ensuring system traceability to international standardsFull-text access may be available. Sign in or learn about subscription options.pp. 471,472,473,474,475,476,477,478,479,480
by S. Max
GLFSR-a new test pattern generator for built-in-self-testFull-text access may be available. Sign in or learn about subscription options.pp. 481,482,483,484,485,486,487,488,489,490
by D.K. Pradhan, M. Chatterjee
Design of an efficient weighted random pattern generation systemFull-text access may be available. Sign in or learn about subscription options.pp. 491,492,493,494,495,496,497,498,499,500
by R. Kapur, S. Patil, T.J. Snethen, T.W. Williams
Efficient test response compression for multiple-output circuitsFull-text access may be available. Sign in or learn about subscription options.pp. 501,502,503,504,505,506,507,508,509,510
by K. Chakrabarty, J.P. Hayes
ECC-on-SIMM test challengesFull-text access may be available. Sign in or learn about subscription options.pp. 511-515
by T.J. Dell
Techniques for characterizing DRAMs with a 500 MHz interfaceFull-text access may be available. Sign in or learn about subscription options.pp. 516,517,518,519,520,521,522,523,524,525
by J.A. Gasbarro, M.A. Horowitz
Automatic failure analysis system for high density DRAMFull-text access may be available. Sign in or learn about subscription options.pp. 526,527,528,529,530
by Sang-Chul Oh, Jae-Ho Kim, Ho-Jeong Choi, Si-Don Choi, Ki-Tae Park, Jong-Woo Park, Wha-Joon Lee
Detection and correction of systematic type I test errors through concurrent engineeringFull-text access may be available. Sign in or learn about subscription options.pp. 531,532,533,534,535,536,537,538
by W.R. Kosar
Defects, fault coverage, yield and cost, in board manufacturingFull-text access may be available. Sign in or learn about subscription options.pp. 539,540,541,542,543,544,545,546,547
by M.M.V. Tegethoff, T.W. Chen
HALT: bridging the gap between theory and practiceFull-text access may be available. Sign in or learn about subscription options.pp. 548,549,550,551,552,553,554
by C. Ascarrunz
Residual charge on the faulty floating gate CMOS transistorFull-text access may be available. Sign in or learn about subscription options.pp. 555,556,557,558,559,560,561
by S. Johnson
Variable supply voltage testing for analogue CMOS and bipolar circuitsFull-text access may be available. Sign in or learn about subscription options.pp. 562,563,564,565,566,567,568,569,570,571
by E. Bruls
Is I/sub DDQ/ yield loss inevitable?Full-text access may be available. Sign in or learn about subscription options.pp. 572,573,574,575,576,577,578,579
by S. Davidson
A software architecture for mixed signal functional testingFull-text access may be available. Sign in or learn about subscription options.pp. 580,581,582,583,584,585,586
by J.A. Masciola, G.K. Morgan, G.L. Templeton
A procedural interface to testFull-text access may be available. Sign in or learn about subscription options.pp. 587,588,589,590,591,592,593
by G.A. Maston
An intelligent software-integrated environment of IC testFull-text access may be available. Sign in or learn about subscription options.pp. 594,595,596,597,598,599,600,601,602,603
by Yuning Sun, Xiaoming Wang, WanChun Shi
Parallel pattern fast fault simulation for three-state circuits and bidirectional I/OFull-text access may be available. Sign in or learn about subscription options.pp. 604,605,606,607,608,609,610,611,612,613
by J.Th. van der Linden, M.H. Konijnenburg, A.J. van de Goor
A hybrid fault simulator for synchronous sequential circuitsFull-text access may be available. Sign in or learn about subscription options.pp. 614,615,616,617,618,619,620,621,622,623
by R. Krieger, B. Becker, M. Keim
Reduced scan shift: a new testing method for sequential circuitsFull-text access may be available. Sign in or learn about subscription options.pp. 624,625,626,627,628,629,630
by Y. Higami, S. Kajihara, K. Kinoshita
An integrated approach for analog circuit testing with a minimum number of detected parametersFull-text access may be available. Sign in or learn about subscription options.pp. 631,632,633,634,635,636,637,638,639,640
by M. Slamani, B. Kaminska, G. Quesnel
Analogue fault simulation based on layout dependent fault modelsFull-text access may be available. Sign in or learn about subscription options.pp. 641,642,643,644,645,646,647,648,649
by R.J.A. Harvey, A.M.D. Richardson, E.M.J.G. Bruls, K. Baker
An analog multi-tone signal generator for built-in-self-test applicationsFull-text access may be available. Sign in or learn about subscription options.pp. 650,651,652,653,654,655,656,657,658,659
by A.K. Lu, G.W. Roberts
Low power mode and IEEE 1149.1 compliance: a low power solutionFull-text access may be available. Sign in or learn about subscription options.pp. 660,661,662,663,664,665,666,667,668,669
by A.L. Crouch, R. Ramus, C. Maunder
An I/sub DDQ/ based built-in concurrent test technique for interconnects in a boundary scan environmentFull-text access may be available. Sign in or learn about subscription options.pp. 670,671,672,673,674,675,676
by Chauchin Su, Kychin Hwang, Shyh-Jye Jou
Fault injection boundary scan design for verification of fault tolerant systemsFull-text access may be available. Sign in or learn about subscription options.pp. 677,678,679,680,681,682
by S. Chau
Ultra hi-speed pin-electronics and test station using GaAs ICFull-text access may be available. Sign in or learn about subscription options.pp. 683,684,685,686,687,688,689,690
by T. Sekino, T. Okayasu
Achieving /spl plusmn/30 ps accuracy in the ATE environmentFull-text access may be available. Sign in or learn about subscription options.pp. 691,692,693,694,695,696,697,698,699,700
by D. Petrich
A test system architecture to reduce transmission line effects during high speed testingFull-text access may be available. Sign in or learn about subscription options.pp. 701,702,703,704,705,706,707,708,709
by M. Mydill
Application of optoelectronic techniques to high speed testingFull-text access may be available. Sign in or learn about subscription options.pp. 710,711,712,713,714,715,716,717,718,719
by E. Sokolowska, B. Kaminska
Back annotation of physical defects into gate-level, realistic faults in digital ICsFull-text access may be available. Sign in or learn about subscription options.pp. 720,721,722,723,724,725,726,727,728
by M. Calha, M. Santos, F. Goncalves, I. Teixeira, J.P. Teixeira
Simulation results of an efficient defect analysis procedureFull-text access may be available. Sign in or learn about subscription options.pp. 729,730,731,732,733,734,735,736,737,738
by O. Stern, H.-J. Wunderlich
The effect on quality of non-uniform fault coverage and fault probabilityFull-text access may be available. Sign in or learn about subscription options.pp. 739,740,741,742,743,744,745,746
by P.C. Maxwell, R.C. Aitken, L.M. Huisman
Application of joint time-frequency analysis in mixed signal testingFull-text access may be available. Sign in or learn about subscription options.pp. 747,748,749,750,751,752,753,754,755,756
by F. Bouwman, T. Zwemstra, S. Hartanato, K. Baker, J. Koopmans
Digitizer error extraction in the nonlinearity testFull-text access may be available. Sign in or learn about subscription options.pp. 757,758,759,760,761,762
by L.S.L. Hsieh, S.P. Kumar
An improved method of ADC jitter measurementFull-text access may be available. Sign in or learn about subscription options.pp. 763,764,765,766,767,768,769,770
by Y. Langard, J.-L. Balat, J. Durand
An on-line data collection and analysis system for VLSI devices at wafer probe and final testFull-text access may be available. Sign in or learn about subscription options.pp. 771,772,773,774,775,776,777,778,779,780
by G.W. Papadeas, D. Gauthier
Test station workcell controller and resource relationship designFull-text access may be available. Sign in or learn about subscription options.pp. 781,782,783,784,785,786,787,788,789,790,791,792
by S.A. Erjavic
Calculating error of measurement on high speed microprocessor testFull-text access may be available. Sign in or learn about subscription options.pp. 793,794,795,796,797,798,799,800,801
by T. Comard, M. Joshi, D.A. Morin, K. Sprague
Goal-directed vector generation using sample ICsFull-text access may be available. Sign in or learn about subscription options.pp. 802,803,804,805,806,807,808,809,810
by D. Raymond, P. Stringer, H. Ng, M. Mitsumata, R. Burk
NAND trees accurately diagnose board-level pin faultsFull-text access may be available. Sign in or learn about subscription options.pp. 811,812,813,814,815,816
by G.D. Robinson
Non-volatile programmable devices and in-circuit testFull-text access may be available. Sign in or learn about subscription options.pp. 817,818,819,820,821,822,823
by D.W. Raymond, D. Haigh, R. Bodick, B. Ryan, D. McCombs
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