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International Test Conference 2007

Oct. 21 2007 to Oct. 26 2007

Santa Clara, CA

Table of Contents

[Copyright notice]Freely available from IEEE.
Table of contentsFreely available from IEEE.
Welcome messageFreely available from IEEE.
Steering Committee and SubcommitteesFreely available from IEEE.
ITC 2006 paper awardsFreely available from IEEE.
Technical Program CommitteeFreely available from IEEE.
ITC technical paper evaluation and selection processFreely available from IEEE.
Call for papersFreely available from IEEE.
Keynote addressFull-text access may be available. Sign in or learn about subscription options.
TTTC: Test technology technical councilFreely available from IEEE.
2007 Technical paper reviewersFreely available from IEEE.
Author indexFreely available from IEEE.
On-chip timing uncertainty measurements on IBM microprocessorsFull-text access may be available. Sign in or learn about subscription options.
by R. Franch, P. Restle, N. James, W. Huott, J. Friedrich, R. Dixon, S. Weitzel, K. Van Goor, G. Salem
Design for testability features of the SUN microsystems niagara2 CMP/CMT SPARC chipFull-text access may be available. Sign in or learn about subscription options.
by Robert Molyneaux, Tom Ziaja, Hong Kim, Shahryar Aryani, Sungbae Hwang, Alex Hsieh
Test cost reduction for the AMD™ Athlon processor using test partitioningFull-text access may be available. Sign in or learn about subscription options.
by Anuja Sehgal, Jeff Fitzgerald, Jeff Rearick
On ATPG for multiple aggressor crosstalk faults in presence of gate delaysFull-text access may be available. Sign in or learn about subscription options.
by Kunal P. Ganeshpure, Sandip Kundu
Silicon evaluation of longest path avoidance testing for small delay defectsFull-text access may be available. Sign in or learn about subscription options.
by Ritesh Turakhia, W. Robert Daasch, Mark Ward, John Van Slyke
Which defects are most critical? optimizing test sets to minimize failures due to test escapesFull-text access may be available. Sign in or learn about subscription options.
by Jennifer L. Dworak
Advancements in at-speed array BIST: multiple improvementsFull-text access may be available. Sign in or learn about subscription options.
by Kevin Gorman, Michael Roberge, Adrian Paparelli, Gary Pomichter, Stephen Sliva, William Corbin
A concurrent approach for testing address decoder faults in eFlash memoriesFull-text access may be available. Sign in or learn about subscription options.
by O. Ginez, P. Girard, C. Landrault, S. Pravossoudovitch, A. Virazel, J.-M. Daga
Diagnosis for MRAM write disturbance faultFull-text access may be available. Sign in or learn about subscription options.
by Chin-Lung Su, Chih-Wea Tsai, Cheng-Wen Wu, Ji-Jan Chen, Wen-Ching Wu, Chien-Chung Hung, Ming-Jer Kao
Data jitter measurement using a delta-time-to-voltage converter methodFull-text access may be available. Sign in or learn about subscription options.
by Kiyotaka Ichiyama, Masahiro Ishida, Takahiro J. Yamaguchi, Mani Soma
New methods for receiver internal jitter measurementFull-text access may be available. Sign in or learn about subscription options.
by Mike P. Li, Jinhua Chen
A selt-testing BOST for high-frequency PLLs, DLLs, and SerDesFull-text access may be available. Sign in or learn about subscription options.
by Stephen Sunter, Aubin Roy
Test-wrapper designs for the detection of signal-integrity faults on core-external interconnects of SoCsFull-text access may be available. Sign in or learn about subscription options.
by Qiang Xu, Yubin Zhang, Krishnendu Chakrabarty
A heuristic for thermal-safe SoC test schedulingFull-text access may be available. Sign in or learn about subscription options.
by Zhiyuan He, Zebo Peng, Petru Eles
Redefining and testing interconnect faults in Mesh NoCsFull-text access may be available. Sign in or learn about subscription options.
by Erika Cota, Fernanda Lima Kastensmidt, Alexandre Amory, Maico Cassel, Marcelo Lubasweski, Paulo Meirelles
Fully X-tolerant combinational scan compressionFull-text access may be available. Sign in or learn about subscription options.
by P. Wohl, J.A. Waicukauski, S. Ramnath
X-canceling MISR — An X-tolerant methodology for compacting output responses with unknowns using a MISRFull-text access may be available. Sign in or learn about subscription options.
by Nur A. Touba
Using timing flexibility of automatic test equipment to complement X-tolerant test compression techniquesFull-text access may be available. Sign in or learn about subscription options.
by Andreas Leininger, Martin Fischer, Michael Braun, Michael Richter, Michael Goessel
Diagnose compound scan chain and system logic defectsFull-text access may be available. Sign in or learn about subscription options.
by Yu Huang, Will Hsu, Yuan-Shih Chen, Wu-Tung Cheng, Ruifeng Guo, Albert Man
A complete test set to diagnose scan chain failuresFull-text access may be available. Sign in or learn about subscription options.
by Ruifeng Guo, Yu Huang, Wu-Tung Cheng
Interconnect open defect diagnosis with minimal physical informationFull-text access may be available. Sign in or learn about subscription options.
by Chen Liu, Wei Zou, Sudhakar M. Reddy, Wu-Tung Cheng, Manish Sharma, Huaxing Tang
Multi-GHz loopback testing using MEMs switches and SiGe logicFull-text access may be available. Sign in or learn about subscription options.
by D.C. Keezer, D. Minier, P. Ducharme, D. Viens, G. Flynn, J. S. McKillop
Analyzing and addressing the impact of test fixture relays for multi-gigabit ATE I/O characterization applicationsFull-text access may be available. Sign in or learn about subscription options.
by Jose Moreira, Heidi Barnes, Guenter Hoersch
Critical roles of RF and microwave electromagnetic field solver simulators in multi-gigabit high-speed digital applicationsFull-text access may be available. Sign in or learn about subscription options.
by Minh Quach, Mark Hinton, Regee Petaja
Testing of Vega2, a chip multi-processor with spare processors.Full-text access may be available. Sign in or learn about subscription options.
by Samy Makar, Tony Altinis, Niteen Patkar, Janet Wu
The design-for-testability features of a general purpose microprocessorFull-text access may be available. Sign in or learn about subscription options.
by Da Wang, Xiaoxin Fan, Xiang Fu, Hui Liu, Ke Wen, Rui Li, Huawei Li, Yu Hu, Xiaowei Li
Design for test features of the ARM clock control macroFull-text access may be available. Sign in or learn about subscription options.
by Frank Frederick, Teresa McLaurin
Analyzing the risk of timing modeling based on path delay tests.Full-text access may be available. Sign in or learn about subscription options.
by Pouria Bastani, Benjamin N. Lee, Li-C. Wang, Savithri Sundareswaran, Magdy S. Abadir
Mining-guided state justification with partitioned navigation tracksFull-text access may be available. Sign in or learn about subscription options.
by Ankur Parikh, Weixin Wu, Michael S. Hsiao
An efficient SAT-based path delay fault ATPG with an unified sensitization modelFull-text access may be available. Sign in or learn about subscription options.
by Shun-Yen Lu, Ming-Ting Hsieh, Jing-Jia Liou
Characterization of NBTI induced temporal performance degradation in nano-scale SRAM array using IDDQFull-text access may be available. Sign in or learn about subscription options.
by Kunhyuk Kang, Muhammad Ashraful Alam, Kaushik Roy
Separating temperature effects from ring-oscillator readings to measure true IR-drop on a chipFull-text access may be available. Sign in or learn about subscription options.
by Zahi Abuhamdeh, Vincent D'Alassandro, Richard Pico, Dale Montrone, Alfred Crouch, Andrew Tracy
Gate delay ratio model for unified path delay analysisFull-text access may be available. Sign in or learn about subscription options.
by Yukio Okuda
Rapid UHF RFID silicon debug and production testingFull-text access may be available. Sign in or learn about subscription options.
by Udaya Shankar Natarajan, Hemalatha Shanmugasundaram, Prachi Deshpande, Chin Soon Wah
A high accuracy high throughput jitter test solution on ATE for 3GBPS and 6gbps serial-ataFull-text access may be available. Sign in or learn about subscription options.
by Yongquan Fan, Yi Cai, Zeljko Zilic
High throughput non-contact SiP testingFull-text access may be available. Sign in or learn about subscription options.
by B. Moore, C. Sellathamby, P. Cauvet, H. Fleury, M. Paulson, M. Reja, L. Fu, B. Bai, E. Reid, I. Filanovsky, S. Slupsky
A stochastic pattern generation and optimization framework for variation-tolerant, power-safe scan testFull-text access may be available. Sign in or learn about subscription options.
by V.R. Devanathan, C.P. Ravikumar, V. Kamakoti
Efficient power droop aware delay fault testingFull-text access may be available. Sign in or learn about subscription options.
by Bin Li, Lei Fang, Michael S. Hsiao
PMScan : A power-managed scan for simultaneous reduction of dynamic and leakage power during scan testFull-text access may be available. Sign in or learn about subscription options.
by V.R. Devanathan, C.P. Ravikumar, Rajat Mehrotra, V. Kamakoti
Implementing bead probe technology for in-circuit test: A case studyFull-text access may be available. Sign in or learn about subscription options.
by Mike Farrell, Glen Leinbach
A bead probe CAD strategy for in-circuit testFull-text access may be available. Sign in or learn about subscription options.
by Kenneth P. Parker, Don DeMille
Impact of Quad Flat No Lead package (QFN) on automated X-ray inspection (AXI)Full-text access may be available. Sign in or learn about subscription options.
by Chwee Liong, Tee, Andy Pascual
Delay defect diagnosis using segment network faultsFull-text access may be available. Sign in or learn about subscription options.
by Osei Poku, R. D. Blanton
Testing for systematic defects based on DFM guidelinesFull-text access may be available. Sign in or learn about subscription options.
by Dongok Kim, M. Enamul Amyeen, Srikanth Venkataraman, Irith Pomeranz, Swagato Basumallick, Berni Landau
Faster defect localization in nanometer technology based on defective cell diagnosisFull-text access may be available. Sign in or learn about subscription options.
by Manish Sharma, Wu-Tung Cheng, Ting-Pu Tai, Y.S. Cheng, Will Hsu, Chen Liu, Sudhakar M. Reddy, Albert Mann
Real-time signal processing - a new PLL test approachFull-text access may be available. Sign in or learn about subscription options.
by Hideo Okawara
A methodology for systematic built-in self-test of phase-locked loops targeting at parametric failuresFull-text access may be available. Sign in or learn about subscription options.
by Guo Yu, Peng Li
An FFT-based jitter separation method for high-frequency jitter testing with a 10x reduction in test timeFull-text access may be available. Sign in or learn about subscription options.
by Takahiro J. Yamaguchi, Masahiro Ishida, Harry X. Hou, Dave Armstrong, Koji Takayama, Mani Soma
Achieving high transition delay fault coverage with partial DTSFF scan chainsFull-text access may be available. Sign in or learn about subscription options.
by Gefu Xu, Adit D. Singh
Fundamentals of timing information for test: How simple can we get?Full-text access may be available. Sign in or learn about subscription options.
by Rohit Kapur, Jindrich Zejda, T. W. Williams
Automated handling of programmable on-product clock generation (OPCG) circuitry for delay test vector generationFull-text access may be available. Sign in or learn about subscription options.
by Anis Uzzaman, Bibo Li, Tom Snethen, Brion Keller, Gary Grise
Programmable deterministic Built-In Self-TestFull-text access may be available. Sign in or learn about subscription options.
by A.-W. Hakmi, H.-J. Wunderlich, C.G. Zoellin, A. Glowatz, F. Hapke, J. Schloeffel, L. Souef
A low cost test data compression technique for high n-detection fault coverageFull-text access may be available. Sign in or learn about subscription options.
by Seongmoon Wang, Wenlong Wei, Srimat T. Chakradhar, Zhanglei Wang
On using lossless compression of debug data in embedded logic analysisFull-text access may be available. Sign in or learn about subscription options.
by Ehab Anis, Nicola Nicolici
Functional testing of digital microfluidic biochipsFull-text access may be available. Sign in or learn about subscription options.
by Tao Xu, Krishnendu Chakrabarty
Enhancing signal controllability in functional test-benches through automatic constraint extractionFull-text access may be available. Sign in or learn about subscription options.
by Onur Guzey, Li-C. Wang, Jayanta Bhadra
Measurement ratio testing for improved quality and outlier detectionFull-text access may be available. Sign in or learn about subscription options.
by Jeffrey L. Roehr
The new ATE: Protocol awareFull-text access may be available. Sign in or learn about subscription options.
by Andrew C. Evans
A matched expansion MEMS probe card with low CTE LTCC substrateFull-text access may be available. Sign in or learn about subscription options.
by Seong-Hun Choe, Shuji Tanaka, Masayoshi Esashi
Management of common-mode currents in semiconductor ATEFull-text access may be available. Sign in or learn about subscription options.
by William J. Bowhers
SPARTAN: a spectral and information theoretic approach to partial-scanFull-text access may be available. Sign in or learn about subscription options.
by Omar I. Khan, Michael L. Bushnell, Suresh K. Devanathan, Vishwani D. Agrawal
A scanisland based design enabling prebond testability in die-stacked microprocessorsFull-text access may be available. Sign in or learn about subscription options.
by Dean L. Lewis, Hsien Hsin S. Lee
A generic and reconfigurable test paradigm using Low-cost integrated Poly-Si TFTsFull-text access may be available. Sign in or learn about subscription options.
by Jing Li, Swaroop Ghosh, Kaushik Roy
Co-development of test electronics and PCI Express interface for a multi-Gbps optical switching networkFull-text access may be available. Sign in or learn about subscription options.
by C.E. Gray, O. Liboiron- Ladouceur, D.C. Keezer, K. Bergman
Finding power/ground defects on connectors — a new approachFull-text access may be available. Sign in or learn about subscription options.
by Kenneth P. Parker, Stephen Hird
IEEE P1581 can solve your board level memory cluster test problemsFull-text access may be available. Sign in or learn about subscription options.
by Heiko Ehrenberg
Statistical analysis and optimization of parametric delay testFull-text access may be available. Sign in or learn about subscription options.
by Sean H. Wu, Benjamin N. Lee, Li-C. Wang, Magdy S. Abadir
Backside E-Beam Probing on Nano scale devicesFull-text access may be available. Sign in or learn about subscription options.
by R. Schlangen, R. Leihkauf, U. Kerst, C. Boit, R. Jain, T. Malik, K. Wilsher, T. Lundquist, B. Kruger
Verification and debugging of IDDQ test of low power chipsFull-text access may be available. Sign in or learn about subscription options.
by M. Laisne, T. Nguyen, S. Zuo, X. Pan, H. Cui, C. Bai, A. Street, M. Parley, N. Agrawal, K. Sundararaman
Low cost automatic mixed-signal board test using IEEE 1149.4Full-text access may be available. Sign in or learn about subscription options.
by Srividya Sundar, Bruce C. Kim, Toby Byrd, Felipe Toledo, Sudhir Wokhlu, Erika Beskar, Raul Rousselin, David Cotton, Gary Kendall
Efficient simulation of parametric faults for multi-stage analog circuitsFull-text access may be available. Sign in or learn about subscription options.
by Fang Liu, Sule Ozev
Using built-in sensors to cope with long duration transient faults in future technologiesFull-text access may be available. Sign in or learn about subscription options.
by C. A. Lisboa, F. L. Kastensmidt, E. Henes Neto, G. Wirht, L. Carro
A novel scheme to reduce power supply noise for high-quality at-speed scan testingFull-text access may be available. Sign in or learn about subscription options.
by Xiaoqing Wen, Kohei Miyase, Seiji Kajihara, Tatsuya Suzuki, Yuta Yamato, Patrick Girard, Yuji Ohsumi, Laung-Terng Wang
Pattern-directed circuit virtual partitioning for test power reductionFull-text access may be available. Sign in or learn about subscription options.
by Qiang Xu, Dianwei Hu, Dong Xiang
California scan architecture for high quality and low power testingFull-text access may be available. Sign in or learn about subscription options.
by Kyoung Youn Cho, Subhasish Mitra, Edward J. McCluskey
Estimating stuck fault coverage in sequential logic using state traversal and entropy analysisFull-text access may be available. Sign in or learn about subscription options.
by Soumitra Bose, Vishwani D. Agrawal
Fast and effective fault simulation for path delay faults based on selected testable pathsFull-text access may be available. Sign in or learn about subscription options.
by Dong Xiang, Yang Zhao, Kaiwei Li, Hideo Fujiwara
Delay fault simulation with bounded gate delay modeFull-text access may be available. Sign in or learn about subscription options.
by Soumitra Bose, Hillary Grimes, Vishwani D. Agrawal
ERTG: A test generator for error-rate testingFull-text access may be available. Sign in or learn about subscription options.
by Shideh Shahidi, Sandeep K. Gupta
ACCE: Automatic correction of control-flow errorsFull-text access may be available. Sign in or learn about subscription options.
by Ramtilak Vemu, Sankar Gurumurthy, Jacob A. Abraham
Modeling facet roughening errors in self-assembly by snake tile setsFull-text access may be available. Sign in or learn about subscription options.
by X. Ma, J. Huang, F. Lombardi
Low cost characterization of RF transceivers through IQ data analysisFull-text access may be available. Sign in or learn about subscription options.
by Erkan Acar, Sule Ozev
An algorithm to evaluate wide-band quadrature mixersFull-text access may be available. Sign in or learn about subscription options.
by Koji Asami
Test yield estimation for analog/RF circuits over multiple correlated measurementsFull-text access may be available. Sign in or learn about subscription options.
by Fang Liu, Erkan Acar, Sule Ozev
Dependable clock distribution for crosstalk aware designFull-text access may be available. Sign in or learn about subscription options.
by Yukiya Miura
Novel compensation scheme for local clocks of high performance microprocessorsFull-text access may be available. Sign in or learn about subscription options.
by C. Metra, M. Omana, TM Mak, S. Tam
A methodology for detecting performance faults in microprocessors via performance monitoring hardwareFull-text access may be available. Sign in or learn about subscription options.
by M. Hatzimihail, M. Psarakis, D. Gizopoulos, A. Paschalis
On the saturation of n-detection test sets with increased nFull-text access may be available. Sign in or learn about subscription options.
by Irith Pomeranz, Sudhakar M. Reddy
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